Even if they did support the max stack per TSMC's ability, you'd need to address other issues even if the bonding was a success. File it under easier said than done in some* applications.They could be testing out higher stacks of things, but keep in mind that the base die has to support connectivity to a specific number of stacks. Zen 3 is likely designed to support a maximum of 4 layers of cache die. HBM has similar limitations with the stacked die supporting pass-through for a limited number of layers. It takes die area for TSVs to support connection to each layer, so going from 4 to 12 might not be trivial. TSMC supposedly has the pitch down to 0.9 microns which is significantly smaller than any micro-solder ball tech, but that is still 900 nm, so tens of thousands of TSVs will still take some area. You also get a higher probability of bonding failure, so they often are not going to use the max except for extremely high end devices. With AMD’s one chiplet for many products strategy, we are likely to only see a limited height stack, not the max TSMC supports.