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Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 6000)

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What do you expect with Zen 4?


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    263

jpiniero

Diamond Member
Oct 1, 2010
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It may be possible than the IOD GPUs are behind monolithic APUs in both assigned die space and performance characteristics since it will be a sort of second class citizen to make use of otherwise empty leftovers, and it will be behind in process technology (All this matching the "entry level performance" claim).
Oh there wasn't going to be any question of that. It likely has no more than 6 CUs. Could be 3.
 
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DrMrLordX

Lifer
Apr 27, 2000
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I believe they're talking about high-end gaming machines, packaging cost won't be an issue there. I couldn't follow the discussion here properly since too many voices equate their needs to the entire mobile sector requirements, generating a lot of interference, but AMD introducing their chiplet based products in the upper range of gaming/productivity oriented "mobile" products would help them compete more easily since A) chiplets will launch first over monolithic APUs and B) total available volume for the mobile market would increase.
Honestly, even high-end gaming laptops would still be better served by designs without an I/O die (or at least a more-efficient one than the ones in Zen2 and 3).
 

coercitiv

Diamond Member
Jan 24, 2014
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Honestly, even high-end gaming laptops would still be better served by designs without an I/O die (or at least a more-efficient one than the ones in Zen2 and 3).
The gamer buying that big notebook with a 200W+ power brick really doesn't care about an extra 5-10W idle power usage of the system, but does care if his rig is using the latest Zen 4 cores instead of Zen 3 with smaller cache. You may think of the I/O die as inneficient, but remember Intel still have theirs outside the package on gaming laptops.
 
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DrMrLordX

Lifer
Apr 27, 2000
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Some TSMC stacking tech, like SoIC, mostly remove the power penalties for using multiple die, so it would be technologically possible (from a power consumption perspective) to make a stacked APU, perhaps with base IO die and cpu/gpu/memory chiplets stacked on top. It just might not be economically feasible to do that vs. a monolithic APU. If they are going to make all of their chiplets to be stacked rather than BGA package mounted, then they have to use stacking everywhere or do two different versions of the chiplet, one for stacking and one for BGA packaging.

The main performance bottleneck being the memory, a monolithic APU with some HBM2e connected via embedded silicon bridge would perform very, very well without using any other stacking. It might be lower power if the HBM is used as a cache for the whole APU to reduce power needed to communicate with off package memory. I kind of doubt that AMD will move to a “stacking only” chiplet with Zen 4, so monolithic APUs will probably be around for a while. Perhaps everything will be stacked with Zen 5.
Oops didn't notice your comment before. I think the only issue with the I/O die of desktop chips is that it just uses a lot of power, period, regardless of how it's oriented in the package. Stacking really isn't going to fix that. The I/O function of the APUs is cut down to save on idle power and total power consumption.

The gamer buying that big notebook with a 200W+ power brick really doesn't care about an extra 5-10W idle power usage of the system, but does care if his rig is using the latest Zen 4 cores instead of Zen 3 with smaller cache. You may think of the I/O die as inneficient, but remember Intel still have theirs outside the package on gaming laptops.
Not sure that the gamer buying one of those laptops is really going to care about an iGPU, either. The OEM might for some reason, but really, when it comes to AMD losing sales from lack of an iGPU on their desktop chips, that isn't the market that comes to mind.
 

Mopetar

Diamond Member
Jan 31, 2011
6,129
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AMD can't serve the market they've already addressed. What's the point in trying to appeal to more?

The whole argument about putting an iGPU on an IO die to address more of the market or appeal to OEMs ignores that AMD already addresses those markets with their line of APUs.

Sure those don't launch at the same time as the desktop parts using chiplets, but the gap between those launches was shortened significantly with Zen 3. Maybe part of that reason is AMD knew they could finally beat Intel so there was an incentive to release the new APUs sooner than they otherwise would.

If Zen 4 is similarly positioned to top Intel's best offering then we may also see AMD launch premium APUs alongside their top desktop products, or at least a lot closer to them. If there's enough of a market that will pay a premium for a top-end AMD APU then they'll probably try to address it assuming they have the wafers to produce enough chips.
 

Thibsie

Senior member
Apr 25, 2017
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I know the market isn't in a normal state but if I had to make a new build right now I would be very happy not having to buy a dGPU and get a functional system with iGPU.
 

jamescox

Senior member
Nov 11, 2009
283
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Oops didn't notice your comment before. I think the only issue with the I/O die of desktop chips is that it just uses a lot of power, period, regardless of how it's oriented in the package. Stacking really isn't going to fix that. The I/O function of the APUs is cut down to save on idle power and total power consumption.



Not sure that the gamer buying one of those laptops is really going to care about an iGPU, either. The OEM might for some reason, but really, when it comes to AMD losing sales from lack of an iGPU on their desktop chips, that isn't the market that comes to mind.
the IO die is still made on GF 12 nm, although I don’t know how much that effects the power consumption for IO . The main issue with power consumption of an APU vs. a chiplet based solution is the extra power for the interface between the IO die and the cpu that is not there in the APU. For a stacked solution, the interface power would be significantly reduced with micro-solder ball style stacking (interposers or embedded silicon bridges). For TSMC stacking tech that doesn’t use micro-solder balls (SoIC), the power consumption could be almost the same as both being on the same die. It would just be more expensive and not all chips need the massive connectivity allowed by SoIC. They could do interesting stuff with this tech, if they have the power budget when stacked. They could possibly have FPGA or gpu units appear like they are internal to the cpu core with this level of connectivity. That runs into severe power limitations though.

I don’t think we are going to see such stacking with Zen 4. Perhaps zen 5 will make more pervasive use of stacking. It could make some sense to have a small gpu on the IO die to support certain features. I brought up the possibility that they may be pad limited on the IO die, which would mean that they would have extra area to fill with something. Having an integrated gpu available in almost all products is a useful feature for many reasons. This would be more likely if is built on a more advanced process than GF offerings.
 
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eek2121

Golden Member
Aug 2, 2005
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the IO die is still made on GF 12 nm, although I don’t know how much that effects the power consumption for IO . The main issue with power consumption of an APU vs. a chiplet based solution is the extra power for the interface between the IO die and the cpu that is not there in the APU. For a stacked solution, the interface power would be significantly reduced with micro-solder ball style stacking (interposers or embedded silicon bridges). For TSMC stacking tech that doesn’t use micro-solder balls (SoIC), the power consumption could be almost the same as both being on the same die. It would just be more expensive and not all chips need the massive connectivity allowed by SoIC. They could do interesting stuff with this tech, if they have the power budget when stacked. They could possibly have FPGA or gpu units appear like they are internal to the cpu core with this level of connectivity. That runs into severe power limitations though.

I don’t think we are going to see such stacking with Zen 4. Perhaps zen 5 will make more pervasive use of stacking. It could make some sense to have a small gpu on the IO die to support certain features. I brought up the possibility that they may be pad limited on the IO die, which would mean that they would have extra area to fill with something. Having an integrated gpu available in almost all products is a useful feature for many reasons. This would be more likely if is built on a more advanced process than GF offerings.
My prediction for desktop is 6nm IOD with iGPU, 1-2x 5nm chiplets. No stacking. Stacked cache? maybe a couple skus? possibly after launch?

From AMD’s remarks, it appears that Zen 3 with stacked cache will be limited to a select few (expensive) skus.
 

jamescox

Senior member
Nov 11, 2009
283
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My prediction for desktop is 6nm IOD with iGPU, 1-2x 5nm chiplets. No stacking. Stacked cache? maybe a couple skus? possibly after launch?

From AMD’s remarks, it appears that Zen 3 with stacked cache will be limited to a select few (expensive) skus.
Milan-x might be exceptionally expensive, but it might be up to 4 layers. They will probably be reserved for HPC, high-end DB servers, etc. The single layer version may be affordable though.

I suspect that a single layer device is actually relatively cheap to make in volume. They are adding extra silicon, but it is a tiny 36 mm2 die. One of them per CCD should be cheap. Using 4 of them is almost 3x the total silicon of the non-stacked part, so I don’t expect those to be affordable at all. The tiny 36 mm2 die size means a huge number of die per wafer and yields are probably good due to some redundancy. Also, it should be cheaper than a cpu wafer. A CPU wafer might require around 12 metal layers for the interconnect. Cache die might be significantly less which means a lower number of mask and a lot lower number of processing steps.

They have talked about gaming performance, so it may be that the cache stacking will actually be very mainstream, at least a single layer. It would be nice to be able to get an 8 core with 96 MB of cache. If they limit it to the 12 and 16 core, then that would put it out of reach of a lot of people. Their 6 and 8 core parts might not be that competitive with intel without it, so hopefully it comes down to 6 and 8 core parts and we finally get some cheaper Zen 3 based parts for the lower end.
 

DrMrLordX

Lifer
Apr 27, 2000
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The main issue with power consumption of an APU vs. a chiplet based solution is the extra power for the interface between the IO die and the cpu that is not there in the APU.
That's partially true, but not entirely. If you look at the x570 chipset:


It's just the I/O die from Matisse. And it can use a lot of power on its own. Granted x570 in particular was on GF 14nm (as opposed to 12nm, for whatever reason; newer x570 boards may have chipsets fabbed on 12nm or even 12LP+) but even still, the power draw of x570 could be a little gnarly:


Over 7W just sitting there, doing nothing? Tell me you don't want that in your mobile chip.
 
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tomatosummit

Member
Mar 21, 2019
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I suspect that a single layer device is actually relatively cheap to make in volume.
While your making a lot of good points I think amd can and certainly will sell it for a lot more than we want, it's still 50% more n7 silicon at best. Unless alderlake smashes it out of the park it's a return to the fx60-64 era prices if we weren't close enough already.
The 6core 3dcache price position doesn't make sense to me but the 5800x is already $400+ and I forsee $600/$800/$1000 kind of costs for the 8/12/16 cores respectiely.
In a nice world it's a +$100 value addition but I know that's not happening.
 

eek2121

Golden Member
Aug 2, 2005
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While your making a lot of good points I think amd can and certainly will sell it for a lot more than we want, it's still 50% more n7 silicon at best. Unless alderlake smashes it out of the park it's a return to the fx60-64 era prices if we weren't close enough already.
The 6core 3dcache price position doesn't make sense to me but the 5800x is already $400+ and I forsee $600/$800/$1000 kind of costs for the 8/12/16 cores respectiely.
In a nice world it's a +$100 value addition but I know that's not happening.
I suspect the 5900X and 5950X will receive an update. Possibly the 5800X.

I also suspect we won’t know about pricing until Alder Lake firms up a bit more.
 

moinmoin

Platinum Member
Jun 1, 2017
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Hmm, surprised they were able to fix that. So all it was doing the entire time was hitting the PCIe link to the CPU?
Not power gating the PCIe I/O area in general I'd think. If you have an X570 or B550 board you can check out the impact by manually disabling link state power management for PCIe in the device manager in the extended energy saving settings (or whatever that's called in English), that should reproduce the earlier reported behavior.
 
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Doug S

Senior member
Feb 8, 2020
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Check the image you inserted more closely. It shows the N7 XR still being sold in June 2021 - and indeed it is still on Apple's site. That will almost certainly be dropped this fall, but they will carry the 11 as their "two years old" model as well as the SE2 which will both require N7P wafer starts through next spring (longer for the SE2 which at the earliest will be upgraded in Spring 2023)

You're also mistaken on the volumes. The iPad, AirPod, and Apple Watch all have higher unit volumes than the Mac. Granted the W* & S* in the latter two are significantly smaller than the M1 so if you go by wafer volume then the iPad the only one that beats the Mac.

Going back to the discussion about which nodes Apple is consuming wafers in I saw yet another product using N7P wafers that looks to be coming from Apple - the replacement to the Pro Display XDR apparently includes an A13 SoC.

OK, so that's quite low volume by comparison (at a guess maybe 100K units a year if Apple is lucky) to everything else I listed, but it shows Apple is constantly looking for places to leverage their A* SoCs as widely as possible, potentially keeping them in production for a long time depending on how often a product is updated - which isn't going to be very often for a display.
 

jamescox

Senior member
Nov 11, 2009
283
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That's partially true, but not entirely. If you look at the x570 chipset:


It's just the I/O die from Matisse. And it can use a lot of power on its own. Granted x570 in particular was on GF 14nm (as opposed to 12nm, for whatever reason; newer x570 boards may have chipsets fabbed on 12nm or even 12LP+) but even still, the power draw of x570 could be a little gnarly:


Over 7W just sitting there, doing nothing? Tell me you don't want that in your mobile chip.
That is, possibly, a good reason to make the IO die on a more advanced process. Although, a lot of that power consumption might be from supporting pci-express 4 speeds. I suspect they will optimize that a lot more going forward such that you don’t get hit with the power penalties unless you are actually running a pci-express 4 device. As far as I know, the mobile APUs don’t support pci-express 4. It isn’t really necessary for consumer and especially with an APU with no GPU. Some of the power optimizations might get ported back to the desktop IO die, but the problem there is that some of those optimizations probably effect performance to save power. You don’t necessarily want that in your desktop system.
 

jamescox

Senior member
Nov 11, 2009
283
505
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I suspect the 5900X and 5950X will receive an update. Possibly the 5800X.

I also suspect we won’t know about pricing until Alder Lake firms up a bit more.
I agree. I don’t think they will set the price until they can see how Intel parts compare. Even though it might be about 116 mm2 7 nm silicon compared to about 80 mm2 7 nm silicon, that doesn’t mean it is going to be 40% more expensive. I suspect yields will be very good and, if something goes wrong in stacking, they can likely still sell it as a part with no L3 cache enabled. I suspect that they will be able to sell them cheaply if they wanted to. The market will dictate the price though. If we are still in a shortage and they can sell every part, then there isn’t much reason to lower the price. I don’t really expect that much of a premium for these with the way they presented them. I think the Epyc parts based on these will be at a big premium though.
 
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