Not on 6nm you aren’t.I'd think if HBM is coming to the CPU that it's to a standalone interposer for something disproportionately larger than anything else. It should be in GB rather than MB at that point. Anything less becomes an overly complicated buffer, not worth the cost. No matter how much bandwidth is there in the chip with HBM attached, it's going to be only a subset of CPU bandwidth. Therefore you can afford to create rows of HBM. This suggests HBM wouldn't come anytime soon in a next step for consumer chip but rather be squarely aimed at EPYC customers where the rectangle shape is necessitated.
On the move to 6nm I think you're going to see a slight increase in core count per chip. They could move to 10, 12, 14, or 16 per die with scaling they've already been working on. They've created architecture that can be scaled as needed.. I know everyone likes iterations in powers of two. But you are no longer bound to filling out groups to the power of 2 on AMDs architecture. They can turn cores on and off at will. And with Infinity Fabric architecture, it's simplified to accomplish these incremental increases into the future.
The layout of the mockups would probably look a bit different IMHO, knowing the two factors above. I could be wrong. But it seems to be evolving in that direction.
Also, AMD will likely stick with 8-core CCDs for the immediate future. Why? Because the cores actually grow in size every generation. AMD has margin targets they want to hit, and adding more cores while simultaneously growing said cores will make the chips more expensive to produce, decreasing margins.
They will likely try to fit additional CCDs on the chip in the future, however.
AMD is excelling by building simple, scalable, flexible designs. Contrast that to Intel, who still hasn’t rolled out chiplets. Compare the number of Ryzen SKUs to Intel SKUs.