This is an older article:I see no reason why you couldn't stack chips made on different processes. All you have to line up are the TSVs, the location of which are independent of process. TSVs connect to the metal layers, and don't care about the location or density of transistors (other than not putting them where a TSV will poke through in chips designed to stack more than two levels high)
I wonder how well TSMC's "SRAM optimized" process scales from N7 to N5? Does it scale as poorly as cache scales on its regular process (where SRAM only gets a 20% scaling from N5 to N3) or does it scale more like logic does on the regular "logic optimized" process (which gets 70% scaling from N5 to N3)
This talk of "cache optimized" processes getting 2x the density for cache versus the standard process is a bit confusing to me. Can someone point to where that claim is made, and how it squares up with Apple's A13? On the A13, which is also made in TSMC 7nm Apple has a 16MB SLC which per Andrei's measurement is 8.47 mm^2 in size. That's basically identical density to AMD's L3 chip with 64MB in 36 mm^2. So is this "cache optimized" thing real, because that's the same density Apple is getting in a standard process. There are different cache types (6T vs 8T cells) and so forth so maybe that accounts for the difference but it is suspicious to me how close the density of the A13 and AMD's L3 chips are.
It list different TSV pitch, but it also says that they might be able to get it down to 0.9 microns from 9 microns on 7 nm and 6 microns for 5 nm. That is almost a year old, so they may have significantly smaller pitch by now. I don’t see why they wouldn’t be able to mix 7 and 5 nm die; they should just need to use a compatible tsv pitch. The 7 nm cache die is presumably a different process presumably from a different line. Mixing something made in a different fab location may be difficult, so that could be a limitation. The cache die is probably a bit cheaper to produce. I doubt that it needs as many metal layers as the full cpu die, so less processing. If we get a 5 nm version of it with Zen 4, then it may be an even larger amount of cache.
This is a much smaller pitch than micro-solder ball solutions so TSMC tech is enabling this for AMD. 9 microns is still 9000 nm though, so this isn’t quite the same as being on the same die, but it is closer than anything else.