- Jan 8, 2001
^Yes! I think it would be a good play to move all L3$ onto a vertical stack for Zen4 (not the L3 controller though). More room for other SRAM structures on the CCD, plus more logic and wider data paths (well, those aren’t taking up space in the floor plan).I outlined previously why AMD should move some L3 off CCD as soon as possible: the CCD uses a process optimized for logic while stacked cache will use a process optimized for SRAM (achieving nearly 2x MB/mm²). You can get more cache in the same total die space by moving the cache out of of the CCD. Sure, stacking adds some cost but when designs are approaching 50% L3 cache by area, a reduction in L3 area could pay off quickly. Or allow them to build a more competitive design to hedge of their stay ahead of their aggressive ARM competitors. Increasing the CCD L3 size is bad economics. But it's easy so maybe they will.