Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[RetroZombie]

They have correctly identified they'll get much more return by spending those same R&D dollar$ on accelerated computing.

That takes too much effort $$$.

The 4S systems 'only' requires:
- a new motherboard for 4S
- Two or three new cpu models* for the 4S boards

*Where only expensive stuff would be released with the 32, 48 and 64 cores, no need for lower count cpu cores models, that would have competition with higher cores count models from the 2S.

Socket would kept the same with the cpu packaged + board giving just a new different redirection.

Besides intel is stuck with 28 cores forever?

 

[DisEnchantment]

With heterogenous computing, chiplets and die stacking either already in place or coming within the next couple of years I have high hopes for FPGAs to be integrated on the system.

One of the reasons Intel is pushing CXL is because of the need to integrate Altera FPGAs properly. Intel is very aggressive on CPU+FPGA integration.
AMD is also part of CXL. There are politics behind CXL but that is not what I want to highlight here.

What is a processor now anyway? Does a FPGA via PCIe not count as an additional processor? Or must it be homogeneous across all sockets?

Exactly what AMD is trying to do!
I did read a lot about of AMD's patents in the area of FPGAs integration with Host CPUs like the sample below.


One of the things they are working on is to have an interconnect mechanism to the host and how the host can schedule work. This is quite typical for an FPGA you might say.
However, bring in HSA and coherency, then the programming paradigm changes and the average programmer can extract performance from these specialized HW.
This is happening already as we speak. The race now is about coherency, interconnects and programming model.

In supercomputing nothing is going to come close to these kind of machines with special purpose FPGAs to accelerate specific workloads, even GPUs cannot come close. You can download an accelerator based on what you are doing.

Dan McNamara who joined AMD and working under Norrod was an SVP at Altera.
If AMD can integrate the Infinity Architecture interconnect slave block on the FPGA and and LUTs can be loaded by the host, you can imagine what an impact this can make.

There are bunch of others things like NVDIMM-P, PIMs (Processing in Memory) which are also areas of intense development in server space.

 

[Topweasel]

They could use 32 lanes to connect to each cpu: 3x 32 = 96 lanes.
Which would leave 32 lanes for pcie connectivity: 4x 32 = 128 board pcie lanes.


That way they could increase the lanes for each socket connectivity or 2x 48 = 96 lanes also leaving 4x 32 pcie lanes free for pcie slots.

Someone here showed how zen internal units are connected this way, couldn't find the post/slides.

Keep in mind that the current config with PCIe 4 lanes has more to do with the requirements of keeping platform compatibility with Naples. So possibly even with 64 cores per CPU, they might be fine with 32 PCIe lanes right now, but can't because of the previous configuration.

In the end if they make any changes to the platform for a 4S setup it might not matter with the IO chip they have a lot more flexibility in deciding how many lanes they want from the CPU for the board and how many they want for each socket to socket connection.

 

[DownTheSky]

Video with full TSMC 5nm lineup. Zen 4 (we already knew this) and RDNA 3 on 5nm.

 

[YAYgee]

https://twitter.com/x/status/1265256141853884416

A bit disappointing wrt Cezanne, still Vega. After Cezanne the focus will shift to improving the iGPU part. Rembrandt will be the first (desktop) APU with RDNA2 (and Zen 3+: TSMC 6nm, DDR5/LPDDR5, USB4, PCIe 4.0).

 

[Ajay]

Geez, Zen2 refresh, Zen3 refresh. Is AMD sandbagging because Intel is falling so far behind in CPU performance and efficiency?

 

[DisEnchantment]

Rampant leakage everywhere, it is nuts. On YouTube, Reddit, Twitter, practically all online PC related Tech media... Zen2 Refresh, Matisse 2, Zen3+, Ryzen3K XT, Big Navi, myriad of codenames... and credible info from legit leakers (rogame, Komachi et al) are drowned in this click farming frenzy.
AMD leaks are eclipsing everything else.

 

[soresu]

Surprised no one got the Raphael thing on Techpowerup, seems like it will be the Zen4 AM5 DT successor to Vermeer.

Cezanne being Vega 2 makes no sense though, unless maybe it's a ULP APU perhaps and Van Gogh is the main one.

 

[YAYgee]

Surprised no one got the Raphael thing on Techpowerup, seems like it will be the Zen4 AM5 DT successor to Vermeer.

Cezanne being Vega 2 makes no sense though, unless maybe it's a ULP APU perhaps and Van Gogh is the main one.

Not according to igorslab and Igor expects Van Gogh to be released at the end of this year.

 

[ksec]

Van Gogh seems like a perfect match for MacBook Air. Although that is up against TigerLake

 

[Ajay]

Rampant leakage everywhere, it is nuts. On YouTube, Reddit, Twitter, practically all online PC related Tech media... Zen2 Refresh, Matisse 2, Zen3+, Ryzen3K XT, Big Navi, myriad of codenames... and credible info from legit leakers (rogame, Komachi et al) are drowned in this click farming frenzy.
AMD leaks are eclipsing everything else.

Hmm. Kinda makes me wonder if AMD some info slip 'on accident'
Could be a setup to catch who's leaking.

 

[maddie]

Hmm. Kinda makes me wonder if AMD some info slip 'on accident'
Could be a setup to catch who's leaking.

Same thought here.

 

[moinmoin]

Since we are in the Zen 4 thread here...

https://twitter.com/x/status/1265256141853884416

A bit disappointing wrt Cezanne, still Vega. After Cezanne the focus will shift to improving the iGPU part. Rembrandt will be the first (desktop) APU with RDNA2 (and Zen 3+: TSMC 6nm, DDR5/LPDDR5, USB4, PCIe 4.0).

The timeline shown in that tweet/article makes no sense.

The description makes Rembrandt sound like a quick Zen 3+ follow up on Zen 3 Cezanne which may make sense considering RDNA1 is clearly a WIP snapshot and RDNA2 was apparently tweaked until close to the next gen console feature freeze, making it missing Cezanne design deadline not unlikely.

But the timeline slide(?) shows Rembrandt as a whole new year after Cezanne, at which time point Zen 4 should be out already, with a Zen 4 APU design soon to follow. That implies that either Zen 4 won't follow the current cadence (being delayed or whatever), or that AMD stops doing the APU designs between each Zen gen designs. I believe neither implication.

 

[DrMrLordX]

Cezanne being Vega 2 makes no sense though

. . . unless it isn't Vega 2 but Vega 3.

 

[RetroZombie]

Maybe it's some old roadmap to catch some leaker(s).

 

[IEC]

Canary trap seems like a possibility.

 

[DisEnchantment]

View attachment 20832
This is AMD's roadmap from 2018 (From momomo_us)

We know some things changed a bit since then,
1. Core
Zen4 Core is planned for Genoa in latest roadmaps (from 2020 FAD) and is no longer the original Zen3 from 2018 roadmap.
View attachment 20839

2. SMT
So AMD did plan 4X SMT for Zen3 after all.
On Genoa, 4X SMT could be real, but could have changed since then. if 3.6+ Gbps HBM is widely available, and cost being manageable for EPYC, the onboard HBM cache could make data closer to the cores and thus SMT efficiency may not be so high.
We know that HBM cache is inevitable, patents indicate this and roadmaps seem to indicate this.
With DDR5 high density, increased speed and double the channels, I hope they continue to raise core counts, to 98C or something. (98C/384T anyone ?)
View attachment 20834

3. Interconnects
Not sure if AMD will use CXL. Probably some form of IOD will take care of this including Gen-Z or CCIX or whatever. But AMD to AMD should be Infinity Architecture. Highly possible that 3rd Gen Infinity Arch relies on PCIe5 Transport.
View attachment 20836View attachment 20837

4. New socket SP5, DDR5, PCIe5 what a coincidence. SP5/DDR5/PCIe5/N5?

6 NVDIMM-P
This is very interesting for me. Samsung and Synopsis did release some PR last year

Synopsys Announces Industry's First DDR5 NVDIMM-P Verification IP for Next-generation Storage-class Memory Designs

Synopsys, Inc. (Nasdaq: SNPS) today announced the availability of the industry's first verification IP (VIP) for Non-Volatile Dual In-line Memory Module (NVDIMM-P) for DDR5/4. NVDIMM-P is the...

news.synopsys.com

This could be the last piece that AMD can put together to address Storage class Memory tech which is another upcoming niche right now and they do have a bunch of new patents on this.
This could be AMD's answer to Optane DC so I am very curious to how it shapes up with DDR5 now on the horizon.

EDIT:
That 64/4 could indicate 4 sockets instead of 4X SMT
The 7nm+ does not indicate it will be on 7nm but rather beyond 7nm. (Official statement)

Well, AMD is going Gen-Z and PCIe over same PHY layer. It is coming

US020200192853 ALTERNATIVE PROTOCOL OVER PHYSICAL LAYER

Abstract
A link controller includes a Peripheral Component Interconnect Express (PCIe) physical layer circuit for coupling to a communication link and providing a data path over the communication link, a first data link layer controller which operates according to a PCIe protocol, and a second data link layer controller which operates according to a Gen-Z protocol. A multiplexer-demultiplexer selectively connects both data link layer controllers to the PCIe physical layer circuit. A protocol translation circuit is coupled between the multiplexer-demultiplexer and the second data link layer controller, the protocol translation circuit receiving traffic data from the second data link layer controller in a Gen-Z format, encapsulating the Gen-Z format in a PCIe format, and passing traffic data to the multiplexer-demultiplexer circuit.

 

[Shivansps]

AMD "Cezanne" APU to Stick with "Vega" iGPU, "Van Gogh" Gets RDNA2

The earliest reports on AMD's next-generation "Cezanne" APU silicon pointed at the possibility of the chip combining "Zen 3" CPU cores with a next-generation iGPU solution based on RDNA2 ("Navi 2#"). AMD plans to launch "Cezanne" in 2021, which makes it the immediate successor to "Renoir." A...

www.techpowerup.com

Let me see if i got this right... Renoir gets replaced next year by Cezzane, also Vega.... not sure why... unless it is Zen3? because LPDDR5 is not going to help much with Vega 8 max, unless the up the GPU CU count, witch i doubt it.

Van Gogh is Dali replacement? so they are launching the small APU replacement with RDNA2 first?

 

[soresu]

AMD "Cezanne" APU to Stick with "Vega" iGPU, "Van Gogh" Gets RDNA2

The earliest reports on AMD's next-generation "Cezanne" APU silicon pointed at the possibility of the chip combining "Zen 3" CPU cores with a next-generation iGPU solution based on RDNA2 ("Navi 2#"). AMD plans to launch "Cezanne" in 2021, which makes it the immediate successor to "Renoir." A...

www.techpowerup.com

Let me see if i got this right... Renoir gets replaced next year by Cezzane, also Vega.... not sure why... unless it is Zen3? because LPDDR5 is not going to help much with Vega 8 max, unless the up the GPU CU count, witch i doubt it.

Van Gogh is Dali replacement? so they are launching the small APU replacement with RDNA2 first?

I agree it is all very odd - I think Van Gogh if not completely custom venture may possibly also be intended for standalone VR use, all those features in RDNA2 would make it ideal for VR.

 

[uzzi38]

I highly doubt Van Gogh is a low power SKU precisely because of the abnormal socket it goes onto.

The idea does not make sense. I'm not ruling it out, but platforms like that are usually in the case where a chip has some sort of very specific feature that wouldn't be shared with a mainstream socket, just as additional memory channels or completely different memory support.

 

[NostaSeronx]

If, Arden and Scarlett are the same. Then, Arden is 14x4 and Scarlett/Anaconda is 13x4.
If, Van Gogh and Mero are the same. Then, Van Gogh is 8x? and Mero is 7x? => Heavy references because of the Subor connection it is 8x3(24 CUs) and 7x3(21 CUs).

It also can be reversed. If, Picasso and Winston are the same. Then, Picasso 10x1(15D8-C1) and Winston is 11x1(15D8-E1).

Van Gogh and Mero appear to be the conjoined successor of Fireflight and Cato. Fulfilling the Office/Game console market that has recently boomed.

Apple Arcade console, the new Subor console(new Subor company?), VCS II(VCS 3200?), etc.

 

[LightningZ71]

Van Gogh still looks like a specific part for Lockhart (Xbox series S). It should hit all the right targets for it.

 

[soresu]

Apple Arcade console, the new Subor console(new Subor company?), VCS II(VCS 3200?), etc.

A second VCS seems extremely unlikely given the first is far too late and costs almost as much as a PS4 Pro, let alone a PS4.

 

[NostaSeronx]

Zen4 or later appears to be a high frequency design ==
Posted on March 11, 2020 & May 27th, 2020; Work with the RTL developers to drive the design to meet an aggressive, high frequency goal while minimizing power.

However don't take it to heart as nothing indicates Zen4 deserves the above language.. since, apparently the current project manager for Zen3/Zen4 is the Boston team. The above was a postion for an Austin cores slot.

So, either it is Zen4 or Zen5 at this current time.

Zen4/5nm is AMD's first true machine learned core&node as well, apparently. So, it might have potential to have high frequency as a target via TSMC's slides on how ML-enhanced EDA increases speed.

 

[soresu]

Zen4/5nm is AMD's first true machine learned core&node as well, apparently. So, it might have potential to have high frequency as a target via TSMC's slides on how ML-enhanced EDA increases speed.

Yeah machine learning based placement of transistors in die design was inevitable.

Hopefully it makes the design stage a little less costly for smaller companies like AMD as it apparently dramatically speeds up the process while achieving on average better results.