Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

[Vattila]

Except for the details about the improvements in the microarchitecture, we now know pretty well what to expect with Zen 3.

The leaked presentation by AMD Senior Manager Martin Hilgeman shows that EPYC 3 "Milan" will, as promised and expected, reuse the current platform (SP3), and the system architecture and packaging looks to be the same, with the same 9-die chiplet design and the same maximum core and thread-count (no SMT-4, contrary to rumour). The biggest change revealed so far is the enlargement of the compute complex from 4 cores to 8 cores, all sharing a larger L3 cache ("32+ MB", likely to double to 64 MB, I think).

Hilgeman's slides did also show that EPYC 4 "Genoa" is in the definition phase (or was at the time of the presentation in September, at least), and will come with a new platform (SP5), with new memory support (likely DDR5).

What else do you think we will see with Zen 4? PCI-Express 5 support? Increased core-count? 4-way SMT? New packaging (interposer, 2.5D, 3D)? Integrated memory on package (HBM)?

Vote in the poll and share your thoughts!

 

[uzzi38]

TBH, the only leaks trustworthy these days are software patches and from shillicon gang, (rogame et al). Going forward those leaks will dry up so bad.

A bit tired of hearing Matisse 2, Zen2+ and Zen3+ roadmaps plucked out of thin air.

Honestly same on that last bit, I was actually on board with what GN was saying for the roadmap until he said the Zen 3+ thing, and it felt like a dud again.

And yeah, best thing to do for now is trust in the benchmark sifters when it comes to leaks. Because amongst other rumours you hear so many different stories it can be difficult to know which one is correct. Outside of the main leakers (_rogame, Komachi, TUM_APISAK, momomo_us, Sharkbay etc) I would be very, very hesitant on taking rumours at face value.

 

[moinmoin]

Both desktop and mobile APUs will be Zen3+ (first mention)

This is quite the non-news considering all Ryzen APUs are improvements on the respective Zen CPU gen. After all that's AMD's whole reasoning behind giving Ryzen APUs the next gen model numbering even though they still use the last gen silicon and node.

 

[Gideon]

A bit tired of hearing Matisse 2, Zen2+ and Zen3+ roadmaps plucked out of thin air.

Honestly same on that last bit, I was actually on board with what GN was saying for the roadmap until he said the Zen 3+ thing, and it felt like a dud again.

This is quite the non-news considering all Ryzen APUs are improvements on the respective Zen CPU gen. After all that's AMD's whole reasoning behind giving Ryzen APUs the next gen model numbering even though they still use the last gen silicon and node.

I understand that skepticism, this was my first reaction as well. IMO what lends it (maybe a bit) more credibility is that he is talking about 2022 APUs not 2021. These APUs apparently also support DDR5 whille Milan should not. Zen 3 APUs will be out in 2021 (so it can't be them). There is also a slim possibility that 5nm is just a bit too expensive for APUs in 2022 and they'll roll with slightly updated Zen3+ on 7nm+(+?). After all they did do it with zen 1.

On the other hand. If the 2022 APUs are indeed 5nm (which IMO they should be) it would be braindead too port Zen 3 there, when Zen 4 already exists on the node. The only reason for Zen3 on 5nm at all would be, if they'll release some (pipe cleaner) APU in 2021 as some TSMC production rumors suggest.

This in-itself is again doubtful (though sure would be excellent) as APUs inherit the compexity of both the CPU and the GPU + complex power delivery between them (with much more focus on power-draw than desktop/server stuff). There is a reason why AMD usually does then last on a node. A GPU is probably still the best bet for the first 5nm product (which will definitely be in 2021)

 

[moinmoin]

These APUs apparently also support DDR5 whille Milan should not.

LPDRR5 maybe, and that again would be pretty much non-news since even Renoir includes an adapted IMC that supports LPDDR4X while Rome does not.

 

[Gideon]

LPDRR5 maybe, and that again would be pretty much non-news since even Renoir includes an adapted IMC that supports LPDDR4X while Rome does not.

I was just referencing what GamersNexus said. He Explicitly mentioned DDR5 and LPDDR5 for Zen3+ APUs.

I'm far from taking this as the unquestionable truth, don't kill the messenger

 

[DisEnchantment]

This is AMD's roadmap from 2018 (From momomo_us)

https://twitter.com/x/status/1257267764189782017

We know some things changed a bit since then,
1. Core
Zen4 Core is planned for Genoa in latest roadmaps (from 2020 FAD) and is no longer the original Zen3 from 2018 roadmap.


2. SMT
So AMD did plan 4X SMT for Zen3 after all.
On Genoa, 4X SMT could be real, but could have changed since then. if 3.6+ Gbps HBM is widely available, and cost being manageable for EPYC, the onboard HBM cache could make data closer to the cores and thus SMT efficiency may not be so high.
We know that HBM cache is inevitable, patents indicate this and roadmaps seem to indicate this.
With DDR5 high density, increased speed and double the channels, I hope they continue to raise core counts, to 98C or something. (98C/384T anyone ?)


3. Interconnects
Not sure if AMD will use CXL. Probably some form of IOD will take care of this including Gen-Z or CCIX or whatever. But AMD to AMD should be Infinity Architecture. Highly possible that 3rd Gen Infinity Arch relies on PCIe5 Transport.


4. New socket SP5, DDR5, PCIe5 what a coincidence. SP5/DDR5/PCIe5/N5?

6 NVDIMM-P
This is very interesting for me. Samsung and Synopsis did release some PR last year

Synopsys Announces Industry's First DDR5 NVDIMM-P Verification IP for Next-generation Storage-class Memory Designs

Synopsys, Inc. (Nasdaq: SNPS) today announced the availability of the industry's first verification IP (VIP) for Non-Volatile Dual In-line Memory Module (NVDIMM-P) for DDR5/4. NVDIMM-P is the...

news.synopsys.com

This could be the last piece that AMD can put together to address Storage class Memory tech which is another upcoming niche right now and they do have a bunch of new patents on this.
This could be AMD's answer to Optane DC so I am very curious to how it shapes up with DDR5 now on the horizon.

EDIT:
That 64/4 could indicate 4 sockets instead of 4X SMT
The 7nm+ does not indicate it will be on 7nm but rather beyond 7nm. (Official statement)

 

[RetroZombie]

So AMD did plan 4X SMT for Zen3 after all.

Why do you think it's smt4? I interpret it has the number of cpu sockets.
4 cpu sockets?

 

[DisEnchantment]

Why do you think it's smt4? I interpret it has the number of cpu sockets.
4 cpu sockets?

This is most likely the correct interpretation! Current EPYCs can only do 2 sockets. Thanks for the interesting hint.


Additionally, according to that roadmap tapeout should happen this quarter for Genoa.

 

[ksec]

So Genoa is Zen 3 and not Zen 4?

 

[DisEnchantment]

So Genoa is Zen 3 and not Zen 4?

No this was a leaked roadmap from 2018. In 2019 they changed to Zen4 when it became apparent they can deliver Zen4 on time.(it could also be that Genoa got pushed to match Zen4/DDR5/PCIe5 timelines)

 

[ksec]

No this was a leaked roadmap from 2018. In 2019 they changed to Zen4 when it became apparent they can deliver Zen4 on time.(it could also be that Genoa got pushed to match Zen4/DDR5/PCIe5 timelines)

I recently ( about a week ago ) saw some Japanese and Chinese media circulating Zen 4 would have SMT 4. I couldn't understand where they got that idea from, now I get it as it was the exact same picture you posted.

I am not sure why 4 Socket would make more sense. On one hand the Market for it is rather small, on the other hand I am wondering if it is due to Intel price segmentation so people prefer 2 Socket. But judging Intel working towards 8S may be 4S do make sense.

 

[DisEnchantment]

I recently ( about a week ago ) saw some Japanese and Chinese media circulating Zen 4 would have SMT 4. I couldn't understand where they got that idea from, now I get it as it was the exact same picture you posted.

I am not sure why 4 Socket would make more sense. On one hand the Market for it is rather small, on the other hand I am wondering if it is due to Intel price segmentation so people prefer 2 Socket. But judging Intel working towards 8S may be 4S do make sense.

I could imagine it could be for compute density per blade. 4S will allow 4x CPUs and a lot of memory and PCIe devices/GPUs hanging off them. Good for high performance clusters. Intel price segmentation also could be a reason.

 

[soresu]

I recently ( about a week ago ) saw some Japanese and Chinese media circulating Zen 4 would have SMT 4. I couldn't understand where they got that idea from, now I get it as it was the exact same picture you posted.

I am not sure why 4 Socket would make more sense. On one hand the Market for it is rather small, on the other hand I am wondering if it is due to Intel price segmentation so people prefer 2 Socket. But judging Intel working towards 8S may be 4S do make sense.

4S does make sense considering that Intel can be behind on cores per socket but make up the difference (or near) in cores per rack because of the difference in sockets.

With 4S, even the current EPYC 2 packages would be able to field 256C 512T per rack, and likely twice that if they double the core count with Zen4 as I believe they will - render power intensifies

 

[RetroZombie]

They might release some 8000 or 9000 series epyc for 4S systems.

This article shows how to get free pcie lanes to be used for other things:
Why AMD EPYC Rome 2P Will Have 128-160 PCIe Gen4 Lanes and a Bonus

Also some Frankenstein epyc with rdna or cdna chiplets on the same package for some 10000 series would be their topnotch premium line.

They don't seem to get enough market share from intel, so they need to go after the premium and differential products even if they all end up being a niche.

 

[moinmoin]

I am not sure why 4 Socket would make more sense.

Infinity Architecture. It's all about interconnecting multiple devices. Having the bandwidth for only two sockets doesn't cut it anymore in that regard. My guess is that the once more bandwidth doubling in PCIe 5 covers that, i.e. Epyc stays at 128 PCIe lanes, but with PCIe 5 the available bandwidth is sufficient to make 4S systems possible (among others => "Infinity Architecture").

 

[Topweasel]

This is a great point. Right now they are using 64 lanes from each CPU for 2S systems. A 4S system would require 3 connections from each CPU. Would make perfect sense at PCIe 5.0 they could probably do it in 16 Lanes per connection with same bandwidth.

Also they could also do whatever they want with io die and toss in a bunch more PCIe specially if it gets a process shrink at some point.

 

[soresu]

This is a great point. Right now they are using 64 lanes from each CPU for 2S systems. A 4S system would require 3 connections from each CPU. Would make perfect sense at PCIe 5.0 they could probably do it in 16 Lanes per connection with same bandwidth.

Also they could also do whatever they want with io die and toss in a bunch more PCIe specially if it gets a process shrink at some point.

Could it not be done with a single bidir connection per socket and a motherboard level IO switch chip like a sort of fractal arrangement of the Ryzen/EPYC IOD and CCD's?

That also sounds like the ideal way to deal with this new Infinity Architecture without blowing the per socket IOD size sky high for dealing with 4S and 8 CDNA boards per rack.

 

[maddie]

Could it not be done with a single bidir connection per socket and a motherboard level IO switch chip like a sort of fractal arrangement of the Ryzen/EPYC IOD and CCD's?

That also sounds like the ideal way to deal with this new Infinity Architecture without blowing the per socket IOD size sky high for dealing with 4S and 8 CDNA boards per rack.

Would that have the same maximum total possible data transfer rate?

 

[soresu]

Would that have the same maximum total possible data transfer rate?

Not a clue, just wondering out loud.

 

[LightningZ71]

That motherboard level I/O chip will introduce even more latency, which is something that AMD is currently at a disadvantage with already. If they were able to keep sufficient intersocket bandwidth for 64 cores per socket at PCIe 4.0 with 64 lanes, then doubling at PCIe 5 would allow them to do two links at 32 lanes for the same total throughput. That would leave a square arrangement and 256 external PCIe lanes. That's a LOT of lanes to sort into PCIe slots and would be just miserable to route.

If they instead used an existing set of 32 lanes to do diagonal connects on the opposite corners of the square, giving every socket a direct connection to each other socket, without increasing the total socket PCIe lane count, that still leaves 192 total outward facing PCIe 5.0 lanes, and maintains current levels of intersocket bandwidth. It also doesn't make the in out of the I/O die significantly more complex, and keeps the socket total pinout manageable. Without increasing core count, that's a 4P system with 256 cores. If they take advantage of the density improvements at 5nm and decide to go for a 12 CCD layout, that's 96 per package, and 384 cores for a 4P system, with 768 threads... jimminey crickets!

 

[DisEnchantment]

Looking at this diagram though, it could possibly indicate that AMD don't see 4S in the near future, or this is just an illustration?
Strange though considering they mentioned 8 way GPU connectivity.
mmmm

 

[RetroZombie]

Would make perfect sense at PCIe 5.0 they could probably do it in 16 Lanes per connection with same bandwidth.

They could use 32 lanes to connect to each cpu: 3x 32 = 96 lanes.
Which would leave 32 lanes for pcie connectivity: 4x 32 = 128 board pcie lanes.

Could it not be done with a single bidir connection per socket and a motherboard level IO switch chip like a sort of fractal arrangement of the Ryzen/EPYC IOD and CCD's?

That way they could increase the lanes for each socket connectivity or 2x 48 = 96 lanes also leaving 4x 32 pcie lanes free for pcie slots.

Someone here showed how zen internal units are connected this way, couldn't find the post/slides.

 

[moinmoin]

View attachment 20921

Looking at this diagram though, it could possibly indicate that AMD don't see 4S in the near future, or this is just an illustration?
Strange though considering they mentioned 8 way GPU connectivity.
mmmm

The focus of Infinity Architecture's introduction was the interconnection of GPUs, as the whole slide shows. The CPUs are just there as supporting actors. I'm sure after Infinty Architecture expands the inter GPU connections CPUs at some point will be able to make use of it as well, if not from the start.

 

[soresu]

That motherboard level I/O chip will introduce even more latency, which is something that AMD is currently at a disadvantage with already.

Depends on your use case, plenty of loads that aren't so latency sensitive as gaming.

 

[Atari2600]

The market for 4-8P* systems is getting smaller and smaller. I don't think there is any point AMD devoting any of their finite resources in that direction. They have correctly identified they'll get much more return by spending those same R&D dollar$ on accelerated computing.

The market is heading toward either 1/2P or big iron/supercomputers, both having the ability to hang multiple co-processors off the architecture.


What is a processor now anyway? Does a FPGA via PCIe not count as an additional processor? Or must it be homogeneous across all sockets?