Speculation: Ryzen 4000 series/Zen 3

[Richie Rich]

**Zen 3**
**Milan**
A0 sampling with no SMT
B0 silicon delayed until September

AMD disabled SMT in microcode for obvious reason: there is SMT4. It would leak out if they wouldn't do that

And because Zen3's new uarch is based around SMT4 and strong FPU, this early leak would ruin current Zen2 sales.

 

[Thunder 57]

AMD disabled SMT in microcode for obvious reason: there is SMT4. It would leak out if they wouldn't do that

And because Zen3's new uarch is based around SMT4 and strong FPU, this early leak would ruin current Zen2 sales.

At this point I don't know if you're being serious or just trying to stir the pot...

 

[Saylick]

That's... pretty tame.

To be honest, given Adored's history of "over promise and under-deliver", I'd rather hear rumors that sandbag the performance and then be pleasantly surprised at launch. My own expectations are +/-15% performance uplift across the board (IPC + clocks), which is in-line with AMD's own road map for >7% CAGR in performance.

 

[Saylick]

AMD disabled SMT in microcode for obvious reason: there is SMT4. It would leak out if they wouldn't do that

And because Zen3's new uarch is based around SMT4 and strong FPU, this early leak would ruin current Zen2 sales.

Richie, if you're so sure about SMT4 being a part of Zen 3, would you be willing to eat a can of cat food if Zen 3 ends up NOT having SMT4? It's only tradition around these parts of town...

 

[Markfw]

At this point I don't know if you're being serious or just trying to stir the pot...

He has always maintained this opinion, just another excuse to say it.

 

[AnandThenMan]

~10% IPS uplift seems reasonable to me any more is gravy IMO.

 

[uzzi38]

AMD disabled SMT in microcode for obvious reason: there is SMT4. It would leak out if they wouldn't do that

And because Zen3's new uarch is based around SMT4 and strong FPU, this early leak would ruin current Zen2 sales.

SMT4 was trimmed from Milan. It was planned originally, it's now gone entirely. Has been gone for a long time now even.

I'm kinda disappointed nobody's seen the real glaring red flag in this "leak". How come nobody's pointed out that initial sampling almost a year after tapeout does not happen?

Milan has been sampling since around November. Maybe a month or two earlier.

 

[DisEnchantment]

I'm kinda disappointed nobody's seen the real glaring red flag in this "leak". How come nobody's pointed out that initial sampling almost a year after tapeout does not happen?

I replied to you on /r/amd but doing again on here

AdoredTV re-LEAKED !!!! the six months old info from reddit
https://www.reddit.com/r/Amd/comments/ddc5kl/zen3_is_ddr4_pcie4_sp3compatible

In that video the AMD rep presenting showed they taped out in Q2 2019 and he mentioned verbally that they are currently sampling (that was in Oct 2019)
The rest of the info he plagiarized from AMD's own Financial Analyst day and call it his own info.

Then went on to say things like yeah SMT was broken on the ES... really???
It is like AMD went to fab without simulation of a synthesizable RTL code and discovered after tapeout functional errors
10-15% IPC, I bet anyone can see that.
I bet he will create another video in some time to cover the other end of the spectrum so that his leaks will cover everything in between.

Jeez man.

 

[uzzi38]

I replied to you on /r/amd but doing again on here

AdoredTV re-LEAKED !!!! the six months old info from reddit
https://www.reddit.com/r/Amd/comments/ddc5kl/zen3_is_ddr4_pcie4_sp3compatible

In that video the AMD rep presenting showed they taped out in Q2 2019 and he mentioned verbally that they are currently sampling (that was in Oct 2019)
The rest of the info he plagiarized from AMD's own Financial Analyst day and call it his own info.

Then went on to say things like yeah SMT was broken on the ES... really???
It is like AMD went to fab without simulation of a synthesizable RTL code and discovered after tapeout functional errors
10-15% IPC, I bet anyone can see that.
I bet he will create another video in some time to cover the other end of the spectrum so that his leaks will cover everything in between.

Jeez man.

Oh, that's you... I didn't have a clue on your username on Reddit till now haha. Noted.

But yeah, I can't say I was happy about this. Talpss half hyped me up the day before as well, can't believe this is all it was. :/

Was really hoping the stuff today was about VGH, because it's weird.

Back on topic, I mean, they've stumbled across some things that might be right? IPC gains with Zen 3 are likely extremely dependant on workload, so as low as 10-15% I can see them saying just to be cautious. Q4 2020 for Milan is fine as well.

Does that mean there was a delay? Nah.

 

[amrnuke]

**Zen 3**
Late 2020 launch, or possibly Q1 2021
SMT2
10-15% ST IPC gain
Shared 32 MB L3 across 8 core CCX
47 cycle latency for the shared L3 (vs 40 cycles for the 16 MB L3 in Zen 2)
New ISA and better security
Power efficiency improvements
Higher boost clocks

Re: N7P vs N7+, I think it would be smarter to drive the nail in the coffin quickly and steal as much gain now as they can, from a business and market standpoint.
IPC gain is in line (even a little lower) than what AMD have publicly stated.

Talking about speculation specific to this "rumor":

- I think the CCX shared cache is interesting, and if they can actually keep latency that low on an 8 core CCX / 32MB L3$ then this will be great (there was a 5 cycle hit from Zen+ to Zen 2 for doubling the L3$ size). I worry about the page-walking TLB penalty unless they rework that, because approaching 16MB in the L3$ you start to see penalties getting supra-exponentially problematic.

- 10-15% ST IPC gain when only 7% performance (at iso-power) is to be gained from N7P (or 10% on N7+) is remarkable, when you consider they expect power efficiency improvements. That means there is probably a lot more uarch magic than they are letting on.

- The combination of efficiency gains + IPC gains + increased boost clocks leads me to believe that, if this rumor is true, this is more likely to be on N7+, but I'm not a chip engineer.

 

[inf64]

I agree with DisEnchantment, this seems like a collection of old rumors. The tape out date does not match the suggested state of A0 silicon nor the rumored IPC increase (in light what Norrod said about Zen3). The lack of leaks tells me that AMD is keeping super tight lid on the ES that are circulating.

 

[lobz]

Yeah, I still expect 20%+ IPC for Zen 3 over Zen 2 based on what Forrest Norrod said. 10-15% would be a major disappointment, at least for me. The rest of the rumor seems plausible, except for the 5 month gap between A0 and B0. I don't suppose it should take 5 months to fix SMT.

I'm assuming bigger IPC gains in areas Zen is still struggling a bit, and only minor improvements where it already excels, and the vast average to be between 10-15%.
If it turns out that way, it could feel as a bigger improvement than what an average IPC gain number tells at first sight.

 

[lobz]

I agree with DisEnchantment, this seems like a collection of old rumors. The tape out date does not match the suggested state of A0 silicon nor the rumored IPC increase (in light what Norrod said about Zen3). The lack of leaks tells me that AMD is keeping super tight lid on the ES that are circulating.

If what you get back from tapeout is severely flawed (however promising its performance may be), it can be a long time before it hits A0 and starts sampling.

 

[uzzi38]

If what you get back from tapeout is severely flawed (however promising its performance may be), it can be a long time before it hits A0 and starts sampling.

If that's the case, it wouldn't be A0 silicon that just started sampling recently. It would be A1 silicon.

If your A0 silicon is borked and you don't want to send it out (though, unless it's something extremely critical that's broken you still would sample it), you prepare A1 silicon that fixes those things.

 

[uzzi38]

Now, bit of an interesting side-topic, but in the past I've mentionned an APU called Van Gogh. Not much was known about it aside from the fact that it's Zen 2 + RDNA2.

Well, as of not-too-long-ago we did find out more information.

1. The CU count is a multiple of 8.
2. Van Gogh and Mero are identical to one another. Or perhaps it would be more specific to say there's strong evidence to believe that one is a derivative off the other.

Neither seem to be any sort of console APU... is something that is publically known but as for how we know it, that information isn't publically available anymore. No it is not part of that Github leak the other day, but uh, rather a much older one that AMD cleaned up as a direct effect of the bad one.

That's all the confirmed info there is. Past that is not-so-confirmed-stuff like what the actual CU count is and customers, but uh, you could probably guess who the customers are rumoured to be if you realised the above specs make Van Gogh some kind of premium APU.

The reason why I won't be talking about said rumour is that is doesn't sound like AMD. Not in the slightest. I won't say that the rumours involve a complete waste of die space, but the iGPU side is too large to make sense given it's AMD we're talking about. It's plausible for a semi-custom project that has a derivative made off of it after other customers show interest in it, but still a bit suspect.

Also we know for a fact that this is the last APU that will have any different to 10-12 CUs per shader array. Which is nice to know too.

EDIT: Oh, one last thing. Bit of speculation from me. If Van Gogh actually is as above and aimed at laptops, I suspect it will be the reasy why there are -HS skus but no -US skus. It would make sense as a 28W part, you know, like how Intel's old 28W chips had a clear focus on iGPU while the CPU side was mostly the same? Take Coffee Lake-U for example.

It's worth noting -S doesn't necesssrily mean low power. It actually refers to the fact that AMD work closely in the design of any laptops with a -S chip.

That... probably gives away one of the customers in the aforementionned rumour too.

 

[RetroZombie]

Now, bit of an interesting side-topic, but in the past I've mentionned an APU called Van Gogh. Not much was known about it aside from the fact that it's Zen 2 + RDNA2.

Even with renoir around it would make sense what you say.
Something with the zen2+rdna2(12cu/16cu), maybe pcie4 for the nvme and another big maybe for DDR5/LPDDR5 imc.

Vega (v3?) inside renoir probably is as efficient as RDNA1 but RDNA2 is at another league in features and efficiency, just do another apu with rdna2 and still zen2, just for microsoft or apple or ...

 

[uzzi38]

Even with renoir around it would make sense what you say.
Something with the zen2+rdna2(12cu/16cu), maybe pcie4 for the nvme and another big maybe for DDR5/LPDDR5 imc.

Vega (v3?) inside renoir probably is as efficient as RDNA1 but RDNA2 is at another league in features and efficiency, just do another apu with rdna2 and still zen2, just for microsoft or apple or ...

I don't think the core count will increase. Sorry, I edited it in just now, but the way I see it Van Gogh makes the most sense as a 28W SKU. If AMD are doing that, then staying with 8 cores makes the most sense due to power budget.

Maybe we might see L3 cache get bumped up? Idk about cache. Extra cache has it's benefits after all (not just on CPU-side, but iGPUs can access L3 cache as well).

But then, that would also have a negative effect on idle power, which is crucial for battery life and makes no sense for a premium device.

 

[RetroZombie]

the way I see it Van Gogh makes the most sense as a 28W SKU

And the other way around? Cut down to 4 cores and 10W or less?
They don't have the intel resources nor market share, otherwise cut down renoir even with raven still around would also make perfect sense too.

 

[uzzi38]

And the other way around? Cut down to 4 cores and 10W or less?
They don't have the intel resources nor market share, otherwise cut down renoir even with raven still around would also make perfect sense too.

In that case RDNA2 makes no sense. Why bother with new and vastly improved uArch on the iGPU for a low TDP product?

Vast majority of the market doesn't care for iGPUs - just very specific customers do.

 

[RetroZombie]

In that case RDNA2 makes no sense. Why bother with new and vastly improved uArch on the iGPU for a low TDP product?

Vast majority of the market doesn't care for iGPUs - just very specific customers do.

Microsoft with their 2-1 systems, lower the cpu core count to save power, rdna2 just for efficiency or cut power too.

 

[uzzi38]

Microsoft with their 2-1 systems, lower the cpu core count to save power, rdna2 just for efficiency or cut power too.

They'll just use Renoir there if anything. I'm talking more for like a Surface Laptop 4 as an example.

 

[RetroZombie]

They'll just use Renoir there if anything. I'm talking more for like a Surface Laptop 4 as an example.

Yes i know. But those van goth or cezanne could be higher versions, successors of renoir or cut down versions (or rebrands).
Or is a fact van gogh is eight cores with rdna2?

 

[NostaSeronx]

Or is a fact van gogh is eight cores with rdna2?

So far yes, VGH is 8 Zen2 w/ RDNA2 WGPs.
Mero was set for Surface/Apple => Van Gogh to Picasso, Mero to Winston

Dali ~150 mm2 => Renoir ~150 mm2 => Cezanne ~125 mm2(just a guess)
Picasso/Winston ~210 mm2 => Van Gogh/Mero ~230 mm2(just a guess) => Rembrandt ~250 mm2(just a guess)
Durango succeeds Pollock => 75~100 mm2(just a guess)

 

[Glo.]

There are two versions that float around about VGH. That it is 16 CU APU and that it is 24 CU.

I don't believe in second option mainly for obvious reason: RX 5500 XT replacement will have 24 RDNA2 CUs, and there is absolutely no sense for AMD to release APU with such CU count.

If anything VGH has to be below that level in CU count.

Why? Because if by any chance this will not be premium-only part, and might land in mainstream market, it has to be below next generation small dGPU in performance.

The other problem with VGH is that in order to give decent performance level on 16 CUs it has to have HBM2.

And, adding to Uzzi's point I think it gives away completely for whom might this iGPU be. There are two, very specific customers who would enjoy low-power SoC, that have powerful CPU and iGPU side in their lightweight, premium laptops.

And those customers are direct competitors to each other.

 

[NTMBK]

There are two versions that float around about VGH. That it is 16 CU APU and that it is 24 CU.

I don't believe in second option mainly for obvious reason: RX 5500 XT replacement will have 24 RDNA2 CUs, and there is absolutely no sense for AMD to release APU with such CU count.

If anything VGH has to be below that level in CU count.

Why? Because if by any chance this will not be premium-only part, and might land in mainstream market, it has to be below next generation small dGPU in performance.

The other problem with VGH is that in order to give decent performance level on 16 CUs it has to have HBM2.

And, adding to Uzzi's point I think it gives away completely for whom might this iGPU be. There are two, very specific customers who would enjoy low-power SoC, that have powerful CPU and iGPU side in their lightweight, premium laptops.

And those customers are direct competitors to each other.

Could LPDDR5 not provide sufficient bandwidth for a powerful GPU?

But I agree that 24 CUs just seems bonkers. The PlayStation 5 only has 32 CUs, I don't see a laptop APU getting two thirds of the way there. 16 CUs, lower clocks, and LPDDR5 is my guess. That would make Apple very happy.