I however think they can technically do it. They have two paths non-CMT and w/ CMT, 6 ALUs is probably the best given non-CMT.I don't think AMD catches lightening in a bottle twice in such rapid succession.
With CMT-path following closely with Keller's CMT from before K8 days. I rushed it so there is behavior not really properly disclosed.
CMP1 => All resources can be used by a single thread.
CMT2 => Resources are virtually-divided as if there is two cores.
SMT4 => Resources are further virtually-divided per cluster for two threads each.
Dynamically-setted based on prediction/pre-fetch behavior stage.
Beside the retire queue is a discrete op-cache, all 4 threads share a single L0i which might be banked per thread or per cluster. Each SLAQ should coincide with a L0d cache 1/4 to 1/8 the size of L1d.
7.5T to 6T is a 13% loss in performance. With density lost being an unknown. However, this is for the 5nm node "This study shows that 6-track cells (192nm high) and smart routing results in up to 60% lower area than 7.5-track cells in N5 technology. Standard cells have been created for 7.5T and 6T cells in N5 technology (poly pitch 42nm, metal pitch 32nm)." and the 12FFC node "However, there is also a new 6T standard cell library, that pushes density up 1.2X vs the 7.5T library on 16FFC."
DUV to EUV for 7nm to 7nm+ is up to a 20% increase in perf. DUV to EUV also increases routeability from DUV to allow for another 1.2x density. Plus the 7.5T to 6T route can mean more than 44% increased logic density. Family 19h(Zen3) isn't Family 17h(Zen2), so there is a lot more potential given for an IPC boost/Area compression.