- Apr 21, 2017
That would be too much I think; was doing a ballpark area guess late at night.Cache requires 8 transistors for a single bitcell, plus 1 for the access path. (more for tags, but let's just ignore them for now.) So you need at least 9*8*4*1024*1024 ~= 300M transistors for 4MB of cache.
So 9*4*1M= 36M
Compares better than order of magnitude close, as 40M equals difference between (X ± 20M).
On another semi related topic, right now I'm looking at the RWT history of the EV8 tragedy linked by nicelandia.
The IPC gained from going out-of-order is actually quite small; they kept the transistors growth relatively low, from EV5's 9M to EV8's 15M. Adjusting for doubled clockspeed we see the IPC increase is not that big ():
At 300MHz, int/FP for EV5 is: 8/13
For EV6 it would be: 15/24
EV7's transistor budget ballooned, and it clocked to 1.5GHz. At 300MHz the projected IPC (neglecting gains from lower cycle RAM benefits) would be:
So it looks like they turned this into a long core speed demon; something that Bulldozer likely inherited from.
More reading for anyone interested: 1. http://alasir.com/articles/alpha_history/alpha_21364_21464.html 2. http://alasir.com/articles/alpha_history/alpha_21264.html
It would also be interesting to know how many transistors were added during the POWER SMT4 jump.