Question Speculation: RDNA3 + CDNA2 Architectures Thread

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HurleyBird

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Apr 22, 2003
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From own AMD financial number, their CDNA sales is insignificant compared to A100 (not even 10%). So no, except the exascale government deals and one EU supercomputer, AMD GPUs have zero presence in HPC (yet). CDNA3 may change it tho
A100 and CDNA2 are different markets with some overlap. Former is all about AI (low precision flops) while the later is all about HPC (high precision tflops). Most A100 sales are not coming from HPC.
 

Mopetar

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Jan 31, 2011
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It certainly is a possibility and may also explain some rumors that indicated a smaller than anticipated amount of infinity cache.

I'm curious if it will be something where they're trying to advertise 8K gaming capabilities, which would likely need a substantial increase in cache size so as not to bottleneck.

It may also benefit RT performance as that apparently requires some additional memory for the data structures that store that information and being able to keep more of that in cache might help AMD see some gains there as well.
 

Mopetar

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Jan 31, 2011
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The other ones aren't really extra chiplets. I'm assuming they're just calling the v-cache die that gets stacked on the MCD an extra chiplet.

Whether they exist or not is another matter, but it makes a certain amount of sense as a mid-generation refresh part. Better than the usual 50 MHz boost bump that we've seen in the last.
 
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Saylick

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Sep 10, 2012
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lol. So RDNA 3 teaser is basically like Zen 4 teaser with the Halo demo. "It looks great, doesn't it?"
 

gdansk

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Feb 8, 2011
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K so where the eff is the rumor mill now.

Navi 33 monolithic.

Navi 32/31 Chiplets with 7 total dies? (1+6)

Navi 32 with 9 Chiplets later? (1+8)

Navi 31 with 13 Chiplets later? (1+12)

God these card announcements cannot come soon enough.
isn't this 13 chiplet talk just the stacked cache? 1 gcd + 6 mcd + 6 stacked cache chips. Å says the stacked cache is optional, after all.

Can TSMC stack N5 on N6? I think that may mesh up
 
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Joe NYC

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isn't this 13 chiplet talk just the stacked cache? 1 gcd + 6 mcd + 6 stacked cache chips. Å says the stacked cache is optional, after all.

Can TSMC stack N5 on N6? I think that may mesh up
From various leaks, MCD should be on N6, and stacked cache should also be on N6.

But in general, both N5 and N7 should be eligible for both top and bottom die. But this picture may not be up to date.

In fact, TSMC should be updating its road map at some conference tomorrow.

1661831016756.png
 

DisEnchantment

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Kaluan

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So, any takers on if there will be a "together we advance_PCs part 2" centered around RDNA3 announcement/launch (and possibly Zen4+V-Cache as well, makes most sense TBH)?

Á la how they announced Ryzen 5000, followed by one (part 2) announcing RX 6000, ~2 years ago.

Edit: Maybe they drop another SAM/ReBAR bombshell this time too. Centered around vertical cache coherency (since both families will use it this gen)... or AI acceleration perks on RDNA3 uArch... idk I'm just spitballing nonsense at this point. But I suspect they will want to make another splash.
 
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