Question Speculation: RDNA3 + CDNA2 Architectures Thread

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uzzi38

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Heartbreaker

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Dragon Range? They can make MCM laptop chips now just fine.

That's just the Desktop part with a different name, made for high power laptops with dGPU.

Note that as Desktop part, it has a MUCH smaller GPU (only 2 CU) than the real laptop parts.

As always, there is strong pressure to make everything a small as possible.


Your guesses are not much better (which version of N3 will be used? The "standard" or the "density optimized" or, like it happened already with the current product, customer oriented variants?) Also we don't even know if there is an Infinity Cache but you assume that there will be. Chip stacking may play a role in reducing the costs. In any case, what you say about the costs don't change anything about the target market scenario, or do you think that magically the new CPU and dGPU will keep the existing processes forever?

Those aren't my guesses. It's Semi Analysis detailed work vs your guesses.

Of course they will move on to new processes. But that doesn't mean they are going to pay to do a large increase in transistors, when transistor costs are flat. Your faulty assumption is that they were getting a big increase in transistor budget for free, which they aren't.
 
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leoneazzurro

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That's just the Desktop part with a different name, made for high power laptops with dGPU.

Note that as Desktop part, it has a MUCH smaller GPU (only 2 CU) than the real laptop parts.

As always, there is strong pressure to make everything a small as possible.




Those aren't my guesses. It's Semi Analysis detailed work vs your guesses.

Of course they will move on to new processes. But that doesn't mean they are going to pay to do a large increase in transistors, when transistor costs are flat. Your faulty assumption is that they were getting a big increase in transistor budget for free, which they aren't.

Semi Analysis details many N3 variants and there are also many N5 variants. So area density and transistor cost must be evaluated on the final design. Without knowing this everything is a guess. Otherwise we could not have a 39% increase of transistor density going from N23 to N33 when N7 to N6 theoretical increase is 18% for the logic only.

And, I never said it was for free. Please quote me where I said that. I said that the area dedicated to the GPU was kept constant and that is likely to stay flat. Which also means that costs will go higher, but this we have already seen with N5.
 

Heartbreaker

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And, I never said it was for free. Please quote me where I said that. I said that the area dedicated to the GPU was kept constant and that is likely to stay flat. Which also means that costs will go higher, but this we have already seen with N5.

You listed your guess of minimal increase in price/area, and a BIG increase in transistor density, that equals a big increase in free transistor budget.

When I Pointed this out you just answered with "I put the math there, feel free to use it. ".

You can't pretend you now meant something completely different.
 

Timorous

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We are talking about the APU for laptops which are monolithic so far.

There will come a point where it is cheaper to 3d stack or tile 2 or more smaller dies than to make 1 larger monolithic die on an advanced node. Trying to predict what N3 products will look like is not easy. Look at MI300. 3d stacked and tiled with cache under the cores/shaders.

The tech is there, just needs scaling up.
 

leoneazzurro

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You listed your guess of minimal increase in price/area, and a BIG increase in transistor density, that equals a big increase in free transistor budget.

When I Pointed this out you just answered with "I put the math there, feel free to use it. ".

You can't pretend you now meant something completely different.

Frankly, I never said it was free and that was your assumption only. The simple fact I assumed same area on a new process with higher wafer costs means that die/GPU area cost cost will go up. All die costs will go up. About the transistor increase, yes, it could be big depending on the design choices as demonstrated by actual examples (N23 vs N33) even on a similar node. If you have comprehension issues, please don't push them on others.
 
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Heartbreaker

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Frankly, I never said it was free. About the transistor increase, yes, it could be big depending on the design choices. If you have your comprehension issues, please don't push them on others.

You don't understand the implications of your own math? Based on faulty assumptions as it was, it amounted to a large increase in transistor budget at the same cost.

If you are going to say something like "I put the math there", you should understand the implications of that math.

To spell it out for you, removing your faulty assumptions, just keeping the same area will increase costs significantly, so they won't do that.

And NO, the same does not apply for Phoenix.

Note that 4nm is actually an economical node, with improved transistor economics. Unlike 3nm where Semi Analysis says: "Shrinking finally costs more, Moore's Law is now dead in economic terms"

3nm is a particularly uneconomic node.

Even given the more favorable economics of 4nm, AMD still stayed with a 12 CU design and shrunk the APU by 18% area vs the previous generation.

Given worse transistor economics at 3nm, expect an even greater shrink to contain costs.
 
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leoneazzurro

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You don't understand the implications of your own math? Based on faulty assumptions as it was, it amounted to a large increase in transistor budget at the same cost.

If you are going to say something like "I put the math there", you should understand the implications of that math.

To spell it out for you, removing your faulty assumptions, just keeping the same area will increase costs significantly, so they won't do that.

And NO, the same does not apply for Phoenix.

Note that 4nm is actually an economical node, with improved transistor economics. Unlike 3nm where Semi Analysis says: "Shrinking finally costs more, Moore's Law is now dead in economic terms"

3nm is a particularly uneconomic node.

Even given the more favorable economics of 4nm, AMD still stayed with a 12 CU design and shrunk the APU by 18% area vs the previous generation.

Given worse transistor economics at 3nm, expect an even greater shrink to contain costs.


My talk started from the point that as there are markets where APUs with a powerful iGPU side may have sense, because an APU will have generally lower costs than a CPU+ comparable dGPU*+accessory costs (* comparable dGPU being the lower mainstream class), a Strix Point with 12WGP at similar sizes than Phoenix -which means around up to 200mm^2- could could be entirely in the realms of possibility .
You started denying it first with considerations on BW (and I pointed out the even not using IC there are today already new memory standards offering way higher bandwidth than current solutions) then started attacking the costs not even understanding that the original point (an APU of similar size of current ones costing less than a discrete GPU+separate CPU+all the PCB and accessory costs) was still valid, as considerations about density and transistor costs (which can vary greatly even on the same process but you are negating that) apply also to the discrete components solution, or even worse as there will be some part with low scaling replicated on both CPU and GPU (i.e. memory controllers). And this will be valid not only for AMD but for other players as well (Apple being APU-only in the portable market should be a hint). Not even speaking of other advantages (possibility to implement very small form factors which usually come at a very hefty price premium). It seems You don't understand -or don't want to understand- what I'm saying since the beginning, and I will stop here because at this point this is pratically trolling.
 
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Heartbreaker

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You started denying it first with considerations on BW (and I pointed out the even not using IC there are today already new memory standards offering way higher bandwidth than current solutions)

A future memory standard, that even including an Infinity Cache, would still be inadequate for the previous discussed increase in the APU.

If you are going to theorycraft, it at least needs to stand up to rudimentary analysis.

Unless you can get 200 MB/s of BW, on top of a sizeable Infinity Cache, then proposed increase in the APU makes little sense, just based on being bottlenecked by BW limitations.

then started attacking the costs not even understanding that the original point (an APU of similar size of current ones costing less than a discrete GPU+separate CPU+all the PCB and accessory costs) was still valid,

It's really not valid, and never was, which is why AMD never does this. Because this is false comparison. This is not a niche part meant to compete with more powerful dGPUs. This is the generic mass market part, that must compete on a cost basis against Intel laptop parts going into the majority of laptops where buyers don't care about a more powerful GPU.

If you make a big GPU part for the majority of the market that doesn't care about having a big GPU, then you make an overpriced part that can't compete in this market.


It seems You don't understand -or don't want to understand- what I'm saying since the beginning...

More like you don't understand the full implications of what you are saying.

Most people just buy basic laptops and don't care about GPU at all. AMD's part must economically compete with Intels, so the cost must be contained. Going for a large GPU that most people don't care about, just drives up the cost, and makes it less competitive.

You make the mistake that many on forums do. Assuming what you want, is what everyone wants. Most people aren't looking for more powerful GPUs in their laptop, so this is not a case where a big APU laptop is competing against a more expensive dGPU laptop, it's a case where the more expensive big APU laptop ends up competing against a laptop with a less expensive Intel chip.

You think it's about competing against a dGPU because you want dGPU performance.

Think about it. It's pretty much always been the case that AMD could build a more powerful APU to challenge more dGPUs, but they NEVER do, and it's because big GPU APU is a niche part, not a mainstream part, and the APU needs to be a mainstream part.
 
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maddie

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Compared to 5nm

N3 : - 25<>30% less power - 10<>15% more performance - 1.7X logic density
N3E : - 34% less power - 18% more performance - 1.6X logic density

"Ho says that TSMC's original N3 features up to 25 EUV layers and can apply multi-patterning for some of them for additional density. By contract, N3E supports up to 19 EUV layers and only uses single-patterning EUV, which reduces complexity, but also means lower density."

This means that a N3E wafer has to cost 60% more than a 5nm wafer for equal logic transistor cost.


N3 - $20K : N5 - $16K : N7 - $10K :

For logic, cost/transistor still falling.
 

leoneazzurro

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A future memory standard, that even including an Infinity Cache, would still be inadequate for the previous discussed increase in the APU.

If you are going to theorycraft, it at least needs to stand up to rudimentary analysis.

Unless you can get 200 MB/s of BW, on top of a sizeable Infinity Cache, then proposed increase in the APU makes little sense, just based on being bottlenecked by BW limitations.



It's really not valid, and never was, which is why AMD never does this. Because this is false comparison. This is not a niche part meant to compete with more powerful dGPUs. This is the generic mass market part, that must compete on a cost basis against Intel laptop parts going into the majority of laptops where buyers don't care about a more powerful GPU.

If you make a big GPU part for the majority of the market that doesn't care about having a big GPU, then you make an overpriced part that can't compete in this market.




More like you don't understand the full implications of what you are saying.

Most people just buy basic laptops and don't care about GPU at all. AMD's part must economically compete with Intels, so the cost must be contained. Going for a large GPU that most people don't care about, just drives up the cost, and makes it less competitive.

You make the mistake that many on forums do. Assuming what you want, is what everyone wants. Most people aren't looking for more powerful GPUs in their laptop, so this is not a case where a big APU laptop is competing against a more expensive dGPU laptop, it's a case where the more expensive big APU laptop ends up competing against a laptop with a less expensive Intel chip.

You think it's about competing against a dGPU because you want dGPU performance.

Think about it. It's pretty much always been the case that AMD could build a more powerful APU to challenge more dGPUs, but they NEVER do, and it's because big GPU APU is a niche part, not a mainstream part, and the APU needs to be a mainstream part.

Again. You. Are. Putting. In. My. Mouth. Words. I. Did. Not. Say.
I spoke about the possibility of having 24CU on Strix Point being OK and that I anyway expect iGPU to continue to improve with time, as well as memory technologies.
Have you tried tp estimate the area of 12 WGP RDNA3 on a N3 process? It's well under 100 mm^2 even assuming quite bad scaling.
I told that there are market cases where a reasonably powerful iGPU could kill lower range dGPUs like the 450Mx, which is already possible TODAY. In future, they could kill the like of a RX6400.
You are telling me I said that I want big APUS with mybe 400mm^2 dies competing with midrange GPUs. Which I never did.
You have comprehension issues or you are a troll.
Please stop here.
 
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Heartbreaker

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I spoke about the possibility of having 24CU on Strix Point being OK and that I anyway expect iGPU to continue to improve with time, as well as memory technologies.

24 CUs will double (or greater) the transistor budget over the Phoenix 12 CU GPU.

Double is a LOT, when transistor costs are flat. Don't make an area argument when this is about transistor costs. You keep trying to pretend this is an inconsequential change. When it isn't.

24 CU part is a niche part, when the APU must be a mainstream part.

You are telling me I said that I want big APUS with mybe 400mm^2 dies competing with midrange GPUs. Which I never did.

No, now you are actually putting words in my mouth.

I'm pointing out that you are defending a uneconomical niche parts like 24 CU APU, that I just quoted you defending again in this post.

This whole massive thread has been about those that just see the APU continuing to evolve incrementally to fit in AM5 memory bandwidth, and mainstream costs.

Versus those that believe there will be a sudden dramatic jump to 24 CU, ignoring the inadequate bandwidth and costs that push it out the mainstream. You have clearly landed on this side of the argument.
 

leoneazzurro

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What you are ignoring is that for selling new CPUs and APUs semiconductors companies must offer something incrementally more powerful and/or with more features in time. Otherwise everyone will stick to older technology.
If all that mattered was cost of the die, then Phoenix too would be an useless part, because its die will cost way more than a Rembrandt, even using same amount of CU (which anyway use more transistors than in RDNA2). And why Rembrandt should have used 12 RDNA2 CU? Vega 8 would have been OK, if everything that mattered was die cost and having only to save transistors. So even if by little, Phoenix iGPU must be more powerful than Rembrandt, it does not matter if it's not a huge lead. And the same it's true for Strix Point. It must be more powerful on the CPU side and on the GPU side. And how to do it? You have to add more: more bandwidth, more compute power. That's it. You cannot have more performance out of nothing. And to sell, new CPUs, new APUs and new GPUs must offer more performance. For justifying the purchase.
 

Heartbreaker

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What you are ignoring is that for selling new CPUs and APUs semiconductors companies must offer something incrementally more powerful and/or with more features in time.

Reading comprehension problems? I just said "APU continuing to evolve incrementally", in the post directly over yours (and previous to that as well). It's like you don't even read the posts you react to. Again, the two sides of this argument are those that believe in incremental evolution (like me), and those that believe doubling GPU performance in a generation(like you).

If all that mattered was cost of the die, then Phoenix too would be an useless part, because its die will cost way more than a Rembrandt

No, I already covered the different economics of Phoenix in a previous response to you here: https://forums.anandtech.com/thread...a2-architectures-thread.2589999/post-40938664

Again, it's like you just don't read...
 

leoneazzurro

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Reading comprehension problems? I just said "APU continuing to evolve incrementally", in the post directly over yours (and previous to that as well). It's like you don't even read the posts you react to. Again, the two sides of this argument are those that believe in incremental evolution (like me), and those that believe doubling GPU performance in a generation(like you).



No, I already covered the different economics of Phoenix in a previous response to you here: https://forums.anandtech.com/thread...a2-architectures-thread.2589999/post-40938664

Again, it's like you just don't read...

Lol, you are the one who does not even read, when did I say that doubling the CU would lead to doubling the performance? I said only that the increment must be enough to justify the increase in cost. Again, you are a troll and continually moving the topic (in fact the post you linked where you "explored the economics of Phoenix" does not contain any analysis of Phoenix, even less compared to its predecessor, especially when you omit that N4 has high costs, like N5, so it costs way more than N6). I was really stupid for trying even to discuss with such a subject.
 
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insertcarehere

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Phoenix and Strix Point don't need better iGPUs than Rembrandt to be incrementally more powerful; that's covered by having Zen 4 and Zen 5 CPU cores respectively.

I sure didn't see much gnashing of teeth when Cezanne basically reused Renoir's iGPU. And nor was it particularly poor in sales because of that observation.
 

leoneazzurro

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Lol, just look at AT review of Cezanne to see if there was no "gnashing of teeth".
In any case, there is not only AMD, and both Intel and Apple are going to increase/have increased substantially their iGPUs. But evidently they are idiots.
 
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Heartbreaker

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I don't discuss with trolls who can't read or even understand that the two sentences are perfectly compatible. Good trolling.

You have been vociferously arguing in favor of substantially larger GPU in general, and 24 CU GPU specifically for pages. Using incorrect assumptions about bandwidth, and incorrect assumptions about transistor costs.

Whenever I point out the actual facts, you whine about trolling... :rolleyes:

Correcting you, and pointing out your inconsistencies is not trolling.
 

leoneazzurro

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You have been vociferously arguing in favor of substantially larger GPU in general, and 24 CU GPU specifically for pages. Using incorrect assumptions about bandwidth, and incorrect assumptions about transistor costs.

Whenever I point out the actual facts, you whine about trolling... :rolleyes:

Correcting you, and pointing out your inconsistencies is not trolling.

redacted[/]. I pointed out there are new memory standards TODAY which provide +50% BW than it is available to current APUs in the same form factor, and you still say it's me who was inconsistent about bandwidth. I said that a 24CU APU on N3 is technically possible within the same die size of today's APUs and you started whining about costs which I did not even started mentioning. Always moving the topic. So yes, you are a troll.



Profanity is not allowed in the tech forums.


esquared
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Heartbreaker

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. I pointed out there are new memory standards TODAY which provide +50% BW than it is available to current APUs in the same form factor, and you still say it's me who was inconsistent about bandwidth.

No, I pointed out, that isn't enough BW for the larger GPU under discussion (24 CU).

I said that a 24CU APU on N3 is technically possible within the same die size of today's APUs and you started whining about costs which I did not even started mentioning.

Costs are what drives everything. Again, you just keep viewing facts as a personal attack, instead of learning from them.
 
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leoneazzurro

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No, I pointed out, that isn't enough BW for the larger GPU under discussion (24 CU).

No, there is not enough bandwidth for doubling the performance (today). That does not mean the performance would not increase. And, once the limiting factor would be BW only, and increase of BW of +50% (available with today's tech) would mean +50% performance vs today's APUs.

Costs are what drives everything. Again, you just keep viewing facts as a personal attack, instead of learning from them.

Costs are what drives everything? So basically there is no market for highend CPUs or GPUs, because they cost more to produce? Why does not AMD, or Intel, or Apple, produce only APUs with 4 cores and 2CU/EU/whatever if only production costs are important? Or maybe someone could pay more for a more powerful APU and someone else will not? Just taking a look at what AMD did with its naming system fpr mobile units this year says a lot about their strategy: they are keeping on the market old technology for budget/mainstream options and new tech will be available for who wants/can to pay more. Just that.
 
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Mopetar

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A 24 CU GPU is feasible if there's something that functions like infinity cache to alleviate the memory bandwidth bottleneck from using system memory instead of VRAM. I've been hoping that AMD would develop a shared last level cache between the CPU and GPU that could be utilized by either depending on the workload.

I don't necessarily believe we'll see that in the next generation of products, but it makes sense for them to head in that direction. Although not every user needs or even wants a beefy GPU, there's a segment of the market that wants a decent CPU and an entry-level GPU and AMD being able to offer that all in one package makes it less expensive for the end user and allows AMD to charge somewhere between the cost of the less capable APUs they have now and that CPU+GPU combination that people will purchase instead.

The move to EUV is supposed to reduce the number of mask layers, which should reduce the upfront cost of having a separate product. Theoretically, having this beefier APU means that AMD can cut a lesser APU product down even more which decreases their cost per chip. All they'd be doing is realizing that a single chip can't span the entire market, in much the same way that there are several GPU dies that address different market segments.
 
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maddie

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A 24 CU GPU is feasible if there's something that functions like infinity cache to alleviate the memory bandwidth bottleneck from using system memory instead of VRAM. I've been hoping that AMD would develop a shared last level cache between the CPU and GPU that could be utilized by either depending on the workload.

I don't necessarily believe we'll see that in the next generation of products, but it makes sense for them to head in that direction. Although not every user needs or even wants a beefy GPU, there's a segment of the market that wants a decent CPU and an entry-level GPU and AMD being able to offer that all in one package makes it less expensive for the end user and allows AMD to charge somewhere between the cost of the less capable APUs they have now and that CPU+GPU combination that people will purchase instead.

The move to EUV is supposed to reduce the number of mask layers, which should reduce the upfront cost of having a separate product. Theoretically, having this beefier APU means that AMD can cut a lesser APU product down even more which decreases their cost per chip. All they'd be doing is realizing that a single chip can't span the entire market, in much the same way that there are several GPU dies that address different market segments.
EUV 1st generation has already reached the limit with N3 using dual-patterning for the earliest layers & that's why a less dense N3E was developed. Nigh NA EUV is needed but will not last too long either for single patterning.
 
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Panino Manino

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Any chance that Valve keep RDNA2 for the next Deck?
IMHO RDNA3+ is a waste of transistors.
I would go with a custom 6 core Zen 3 CPU and 16-18CU RDNA2.
Really, I see no reason to chose RDNA3, instead use the extra transistor budget on a bit of IF.