Question Speculation: RDNA2 + CDNA Architectures thread

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uzzi38

Platinum Member
Oct 16, 2019
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All die sizes are within 5mm^2. The poster here has been right on some things in the past afaik, and to his credit was the first to saying 505mm^2 for Navi21, which other people have backed up. Even still though, take the following with a pich of salt.

Navi21 - 505mm^2

Navi22 - 340mm^2

Navi23 - 240mm^2

Source is the following post: https://www.ptt.cc/bbs/PC_Shopping/M.1588075782.A.C1E.html
 

Konan

Senior member
Jul 28, 2017
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Its very simple. If you have inferior product you have two choices.

Either you launch the product before your competition, or after, and adjust prices.

Its simple as that.

With the 3070 price already determined hopefully AMD going after will adjust their prices accordingly and not get as greedy as Nvidia has been on occasion.
 

Konan

Senior member
Jul 28, 2017
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Its not AMD who has to adjust their prices, accordingly ;).
But there is already a couple of strong rumors they have adjusted desired launch pricing ;)
With the 3070Ti and 3060Ti coming there isn't a need for NV to adjust again at the moment from the 3070 announced pricing.
 

TitusTroy

Senior member
Dec 17, 2005
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would it make sense to buy a Big Navi card if I have a 1440p 144hz G-Sync monitor (not FreeSync compatible)?...the monitor (ViewSonic XG2703-GS IPS) is only 2 years old so I have no intention of buying a new one anytime soon
 

NostaSeronx

Diamond Member
Sep 18, 2011
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Unless the GPU has changed from Renoir why give it a different name then?
Green Sardine is the APU's name. It could be for a different market than Lucienne or it is the actual SoC name.

Instead of Grey Hawk, it could be Green Sardine.

0x00, 0x01, 0x21 => Raven_A0, Raven_A1, Raven_B0
0x41 => Picasso_A0

0x91 w/ 1636 => Renoir
0xA1 w/ 1636 => Green Sardine

0x01 => Carrizo
0x10 => Bristol

New transistor implants, new transistor structures, etc.
CZ -> BR => GF28A to GF28HPA
RV_B -> PC_A => GF14LPP to GF12LP

Big change could be RN -> GS is TSMC7FF(P) to TSMC7FFe or TSMC6FF
7FFe makes sense since Renoir was developed with the same node in mind as Ariel(PS5), Arden(XSX), Van Gogh(XSS).
 
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uzzi38

Platinum Member
Oct 16, 2019
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Green Sardine is the APU's name. It could be for a different market than Lucienne or it is the actual SoC name.

Instead of Grey Hawk, it could be Green Sardine.

0x00, 0x01, 0x21 => Raven_A0, Raven_A1, Raven_B0
0x41 => Picasso_A0

0x91 w/ 1636 => Renoir
0xA1 w/ 1636 => Green Sardine

0x01 => Carrizo
0x10 => Bristol

New transistor implants, new transistor structures, etc.
CZ -> BR => GF28A to GF28HPA
RV_B -> PC_A => GF14LPP to GF12LP

Big change could be RN -> GS is TSMC7FF(P) to TSMC7FFe or TSMC6FF
7FFe makes sense since Renoir was developed with the same node in mind as Ariel(PS5), Arden(XSX), Van Gogh(XSS).
Van Gogh is not the Series S APU.

It's 4 cores and 8CUs.
 

Elfear

Diamond Member
May 30, 2004
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would it make sense to buy a Big Navi card if I have a 1440p 144hz G-Sync monitor (not FreeSync compatible)?...the monitor (ViewSonic XG2703-GS IPS) is only 2 years old so I have no intention of buying a new one anytime soon

Depends on how highly you value VRR. Personally I think it's a pretty important feature. Now that Nvidia supports G-Sync compatible monitors, you can choose a good FreeSync 2 monitor that allows you to use team red or team green GPUs. I sold my G-Sync monitor a few years ago so I wasn't locked into one ecosystem.
 

NostaSeronx

Diamond Member
Sep 18, 2011
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Van Gogh is not the Series S APU.

It's 4 cores and 8CUs.
Xbox Series S is Van Gogh.
Family 17h 90h-9Fh is the Van Gogh part. Which in turn Family 17h 98h is the Xbox Series S.

It's 8-cores and 24 CUs.

Arden which is Family 17h 80h-8Fh appears before it, thus we know it is the bigger APU. It happens to be 8-core/56 compute units.

AMD's Renoir has an APU before it as well. However, it was done before the 18h family being fused in family 17h. With 4-cores and 24 CUs. Making it the part that lead to the Xbox Series S/Van Gogh.
 

uzzi38

Platinum Member
Oct 16, 2019
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Xbox Series S is Van Gogh.
Family 17h 90h-9Fh is the Van Gogh part. Which in turn Family 17h 98h is the Xbox Series S.

It's 8-cores and 24 CUs.
It's 4 cores and 8CUs.

I'm not discussing this as a "might be". I'm discussing this in a "I-know-somebody-who-works-with-AMD-directly-and-the-Power-Monitoring-Table-they-have-shows-only-4-cores" way
 

NostaSeronx

Diamond Member
Sep 18, 2011
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It's 4 cores and 8CUs.

I'm not discussing this as a "might be". I'm discussing this in a "I-know-somebody-who-works-with-AMD-directly-and-the-Power-Monitoring-Table-they-have-shows-only-4-cores" way
While, I'm discussing the fact that Microsoft's Xbox Series S has been repeatedly been using the Van Gogh name by Microsoft.

Could there be a die-harvested Van Gogh sure. They had dual-core/3 cu dies of Raven as Athlon 2xxGE/3xxGE. Before, coming out with Raven2 as 3000G.

There is also Cato which was a die-harvested Xbox One S. So, it wouldn't be uncommon for Van Gogh that you are seeing is a die-harvested part.

AMD Side SoC => Microsoft Side SoC
Arden = 80h-8Fh => Xbox Series X APU, "Anaconda" => 100% Arden SoC
Van Gogh = 90h-9Fh => Xbox Series S APU, "Lockhart" => 100% Van Gogh SoC
 

reb0rn

Senior member
Dec 31, 2009
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I can't stand those youtubers they think 2x in size is 2x speed, at same time they forget ray trace and dlss asic will use a LOT of space of the GPU, even then silicon never scale as that
Also we can't forget they did nto go to 384 or 512 bit memory as that is expansive nor for HBM2!
So even then we might presume a lot of transisitors will go to cash! also they do not scale performance as that!
 

BlitzWulf

Member
Mar 3, 2016
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So I'm not one to usually speculate about things I don't understand but I am curious about something .

More than once now I've heard that the die size for Big Navi seems to bee bigger than what would be deemed necessary for what we know and are assuming about the architecture.

Does anyone else think that AMD may be using that extra space for some sort of hardware decompression asic like those found in the consoles?

To my knowledge AMD has been totally silent on this front (and every front to be fair) while almost every other major player in the space has publicly announced some info about how they fit in to the I/O craze of this generation.

Am I way off base here? It seems crazy that AMD would waste that much die space on dark silicon when TSMC 7n+ wafers don't come cheap.
 

Mopetar

Diamond Member
Jan 31, 2011
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would it make sense to buy a Big Navi card if I have a 1440p 144hz G-Sync monitor (not FreeSync compatible)?...the monitor (ViewSonic XG2703-GS IPS) is only 2 years old so I have no intention of buying a new one anytime soon

Guess it really depends on how good big Navi is and what it costs. Between. 3080 at $700 being nearly the best value for your dollar at 1440p and a 3070 that should be quite good itself it's hard not to recommend that if adaptive sync is something you really want.

Some people swear by it over raw frame rates or even maxed out settings so I think it really comes down to your personal preferences. Of course if big Navi really hits it out of the park you could probably do without it if you're willing to lock the frame rate to something it can always deliver. I think their software lets you do that fairly easily.

Hell, you'll probably be able to get gray 1440p performance from a 3060. I think big Navi is going to be aimed at 4K so it might be overkill for what you're looking at.
 
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ModEl4

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Oct 14, 2019
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According to Coreteks the die has 536 mm2 size.
I don't know if he's right or wrong, but in the video he mentions that consoles is on N7+ EUV. Specifically in a previous video he made, he explains how he knows this, and it is an info he got from synopsys web page regarding Xbox SeriesX (Xbox SRAM provider). In a latter video if I remember correctly, he even says he is 100% sure for Xbox SeriesX (and I guess he is speculating that the PS5 will be also). The thing is Xbox SeriesX is not on EUV and he is wrong, also after the first video he made, in the comments someone told him that Microsoft at Hot Chips clarified that it is not on EUV and that the process is N7E and still he keeps saying it😒
 

HurleyBird

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Apr 22, 2003
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He's easily my least favourite techtuber. Others have had bad leaks, and speculation that ended up false, but his reasoning for the traversal processor on the back of Ampere cards was absolutely irrational and made it obvious that he isn't the brightest tool in the shed. The claim of 2080Ti + 15% has always seemed way off to anyone paying the slightest attention. Ninety percent of being a good leaker is separating good info from bad, and that takes a certain amount of intelligence.

That said, if he's seen a picture of the pcb with the bare die, I'm fairly inclined to believe him. I'm assuming he's at least smart enough to know a shopped image when he sees it, I could be wrong.
 

uzzi38

Platinum Member
Oct 16, 2019
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I can't stand those youtubers they think 2x in size is 2x speed, at same time they forget ray trace and dlss asic will use a LOT of space of the GPU, even then silicon never scale as that
Also we can't forget they did nto go to 384 or 512 bit memory as that is expansive nor for HBM2!
So even then we might presume a lot of transisitors will go to cash! also they do not scale performance as that!

There will be no dedicated hardware for AI operations, just packed maths. As for RTRT, it's already established that AMD's method of doing so requires absolutely minimal die space. The entire point of it was area efficiency.

As for performance, better of waiting and seeing how it turns out. As it stands we still don't know for certain.
 

PhoBoChai

Member
Oct 10, 2017
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Yep it *could* be both large cache and die size:

View attachment 30902

Command and Front End is scalable per Xbox, multi-core, multi-streams of commands. They would have to do it for the extra shader arrays in 80CUs.

TMUs also much bigger than RDNA 1 due to fixed function BVH + triangle intersection units.

A few things like that have to be taken into account, along with more interconnect and bus for L2 partitions to the IF.

All in all, 7N+ density allows for a LOT of extra transistors in the rumored 505mm2 die, so AMD has room to grow L1$ and L2$ big time.
 

PhoBoChai

Member
Oct 10, 2017
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There will be no dedicated hardware for AI operations, just packed maths. As for RTRT, it's already established that AMD's method of doing so requires absolutely minimal die space. The entire point of it was area efficiency.

As for performance, better of waiting and seeing how it turns out. As it stands we still don't know for certain.


Yes and NO. RDNA 1 already had modified dual CUs, one per SHA, that can handle tensor ops, aka dot matrix product. Look in the whitepaper.

The huge increase in register per CU/DualCU and shared L1 & LDS in multi-CU means they can link CUs up to handle larger matrixes if required.

So no dedicated tensor cores, but flexible dualCUs, and in RDNA 2, probably with larger shared L1$ (speculation), they can link more dual CUs together to run deep tensor matrixes very fast.