I'd wager more exotic than that - even a chilled liquid cooler might have problems keeping that stable.Got to be at least liquid cooled.
LinkAnd it's 24+64 Still has Infinity Cache.
Im pretty certain that on both ocasions in his info Yuko is wrong in one way or another.Here is some info from Yuko Yoshida about Infinity and memory configs of N22, N23 and N24..
And another one about N24.
What you wrote could be really just a cutdown N23, but It would have the same number of CUs as N24.
N24 could end up with more Vram, but that was already the case with 5500XT vs 5600XT, so It wouldn't be such a surprise.
Im fairly certain that what you wrote, compared to Yuko, is correct.I believe it's 192/128/96 bit bus for Navi 22/23/24 respectively, with Navi 22 also having a 160 bit cutdown config.
IC config should be 96/64/48 MB for N22/23/24, with N22 cutdown having 80MB.
If so then Yes, you are correct.Drivers suggest IC is tied to memory channels, if there is a cutdown 160 bit N22 (6600 XT 10 GB?) then it should have 80 MB IC.
RTX 3090 has 384bit GDDR6x and 24x 1GB GDDR6X chips.Im pretty certain that on both ocasions in his info Yuko is wrong in one way or another.
N24 won't end up with more VRAM, than 6500/XT because 4 GB memory chips have eye watering prices, compared to 2 GB ones.
So its always 6 GB's VRAM.
Well, sure, but that has its own drawbacks. You need to provide cooling on the backside of the GPU.
That raises an interesting question about what's being done with all of the N21 dies with a defective memory controller or infinity cache that necessitates disabling a memory controller. Just from the information we have available the IF and memory controllers account for about 25% of the die space. Although the yields are good, it's still a big die so they should be getting 30-40% defective dies per wafer depending on how much the defect density has changed since TSMC last disclosed it. That's potentially as much as 10 dies per wafer that aren't being sold as even a 6800. I can't see AMD just throwing them out.Drivers suggest IC is tied to memory channels, if there is a cutdown 160 bit N22 (6600 XT 10 GB?) then it should have 80 MB IC.
If the layout is similar to Navi14, then it's because of the placement of dualCU, which is 3 columns and 4 rows of dualCUs for a total of 12 dualCUs. Am I right?All I can tell you at this point is that it is related to the layout of the dies.
I think you'll see the obvious, technical reason for this.
Your post might sound very funny, but it reminded me of this article from semiaccurate several years ago.A Triangle - more area efficient placement on round wafer
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