SPARC M7 -- 4.1GHz, 32-core CPU on TSMC 20nm

[Arachnotronic]

Balanced Design Principles: The new SPARC M7 processor is the design center of the new line of SPARC M7 systems that scale from 32 to 512 cores, 256 to 4,096 threads and up to 8 TB of memory.

https://www.oracle.com/corporate/pressrelease/sparc-m7-102615.html

So, uh, who said TSMC 20nm couldn't be used to build high performance products?

 

[ShintaiDK]

600-700mm2 as well. Huge chip on a high performance 20nm node.

Its all about cost. Easy to see who are the small and big players in the industry.

 

[Arachnotronic]

600-700mm2 as well. Huge chip on a high performance 20nm node.

Indeed. This is an impressive piece of engineering.

 

[witeken]

https://www.oracle.com/corporate/pressrelease/sparc-m7-102615.html

So, uh, who said TSMC 20nm couldn't be used to build high performance products?

Not impossible, but not much benefit besides the 1.9x or so increase in density.

 

[NTMBK]

Not impossible, but not much benefit besides the 1.9x or so increase in density.

Cramming in double the number of cores seems pretty beneficial!

 

[sm625]

If it scales to 512 why even bother with 32?

 

[Arachnotronic]

If it scales to 512 why even bother with 32?

Single socket?

 

[guskline]

What Operating system does it use?

 

[Nothingness]

What Operating system does it use?

Solaris.

The SQL accelerator is intriguing...

 

[fourdegrees11]

8 threads per core?

 

[ShintaiDK]

Accelerators is the new buzz. Skylake on the Purley platform will also introduce more of these.

 

[Nothingness]

Accelerators is the new buzz.

It's not new. In enterprise, IBM started a few years ago with PowerEN (pattern matching accelerator). And I guess we could dig some older experiments

Skylake on the Purley platform will also introduce more of these.

Yeah, can't wait to see what Intel implements.

I wonder how useful these accelerators end up for their target market. HW accelerators can do wonders provided they implement the right functionality, but they can quickly become completely irrelevant (this reminds me of the Amiga blitter that was used to speed up various forms of graphics transfers, and which became slower than the faster processor variants used in later Amiga machines).

 

[Arachnotronic]

I wonder how useful these accelerators end up for their target market. HW accelerators can do wonders provided they implement the right functionality, but they can quickly become completely irrelevant (this reminds me of the Amiga blitter that was used to speed up various forms of graphics transfers, and which became slower than the faster processor variants used in later Amiga machines).

I think that's why Intel wants FPGAs -- so that the accelerator is dynamic

 

[ShintaiDK]

I know its not new, but it is the new buzz

 

[Nothingness]

I think that's why Intel wants FPGAs -- so that the accelerator is dynamic

The problem is two-fold with FPGA, compared to a dedicated engine:
- potentially more loosely coupled that an accelerator, which means more latency, so bigger datasets before their use becomes interesting
- much more power hungry.

But that's much more sexy than hardware accelerators

 

[Hi-Fi Man]

SPARC is getting the squeeze from Power8, especially now that we have OpenPOWER which is bringing some major players to the table (Google, Tyan, Altera, Mellanox, nVIDIA, etc). There's only Oracle and Fujitsu really behind SPARC.

I wonder how this 20nm TSMC node compares to IBM's 22nm SOI node.

On the note of accelerators Power8 also has CAPI and NVLink, not sure if SPARC has any equivalents.

Note my Power bias evident from the avatar...

 

[witeken]

Cramming in double the number of cores seems pretty beneficial!

Not so much at 1.5x power consumption and power density! Maybe even more depending on leakage.

 

[Thala]

Not so much at 1.5x power consumption and power density! Maybe even more depending on leakage.

Double the number of cores for only 1.5x power sounds like a good deal to me.

 

[witeken]

Double the number of cores for only 1.5x power sounds like a good deal to me.

I took 1.9x. 2.0x would be 1.6x, but that's just taking TSMC's 20% drop in power. But I suppose, like companies always do, that that is for low power because those always have the best improvement (e.g. TSMC claims 55% drop for finfet), so it might be more like 10%, who knows.

In any case, TDP is something like 250W I saw, while Intel tops out at ~150W.

 

[Hugo Drax]

Pointless for desktops. You would end up with 512 parked cores for the average user.

 

[Arachnotronic]

Pointless for desktops. You would end up with 512 parked cores for the average user.

This is a specialized server chip.