I've been meaning to do this since I was in college... finally got a friend to run the experiment on a non-NDA process technology (one of the ones used in academia). I don't know exactly how he sized the gates, but for these purposes, whatever he did worked well enough.
http://ctho.ath.cx/pics/ring_oscillator_delay_vs_temperature.png
This shows the performance of a simple circuit at various temperatures. The circuit doesn't include long wires, so scaling of wire resistance won't show up here.
http://ctho.ath.cx/pics/ring_oscillator_delay_vs_temperature_chart.png
Temp (C)__Delay (picoseconds)
100______795.6 ps
50_______676.6 ps
0________566.2 ps
-50______464.2 ps
Alternately, it could run at:
100: 1.25GHz
50: 1.45GHz
0: 1.75GHz
-50: 2.15GHz
I believe these temperatures are the temperatures at the transistors (rather than on the top of the package), so they're highly unlikely to correlate with the temperatures your CPUs report.
Real chips have additional complexities that tend to make the scaling less than ideal (for example, some circuit styles are sensitive to the ratios of the speeds of different transistor types which can change with temperature; other styles are sensitive to the relative delays of gates).
http://ctho.ath.cx/pics/ring_oscillator_delay_vs_temperature.png
This shows the performance of a simple circuit at various temperatures. The circuit doesn't include long wires, so scaling of wire resistance won't show up here.
http://ctho.ath.cx/pics/ring_oscillator_delay_vs_temperature_chart.png
Temp (C)__Delay (picoseconds)
100______795.6 ps
50_______676.6 ps
0________566.2 ps
-50______464.2 ps
Alternately, it could run at:
100: 1.25GHz
50: 1.45GHz
0: 1.75GHz
-50: 2.15GHz
I believe these temperatures are the temperatures at the transistors (rather than on the top of the package), so they're highly unlikely to correlate with the temperatures your CPUs report.
Real chips have additional complexities that tend to make the scaling less than ideal (for example, some circuit styles are sensitive to the ratios of the speeds of different transistor types which can change with temperature; other styles are sensitive to the relative delays of gates).