Something I've always wondered

[imported_Tick]

If so, how do they talk to the processor? Their own FSB? Also, I hear about cache latency, but how much bandwidth does cache have?

 

[luhai]

Cache is just low latency memory. As far as the processor is concerned, L1, L2, RAM are more or less the same except latency. Ars have good article about it.
http://arstechnica.com/articles/paedia/cpu/caching.ars

 

[alpha88]

I'm sure that article will explain it better, but cache is 'transparent' to the CPU. When the CPU reaches a read from memory instruction, the mechanism for reading from memory (RAM) checks the cache for the data at the same time.

This is over simplifying it, but each block in the cache stores a memory address and a value. The CPU basically shouts, does anyone have memory address #52352, and all the cache blocks check themself, and if they do have it, they send it back.

The memory controller on the other hand, translates the memory address into a specific block of the RAM and requests the data stored there.

 

[imported_Tick]

Originally posted by: alpha88
I'm sure that article will explain it better, but cache is 'transparent' to the CPU. When the CPU reaches a read from memory instruction, the mechanism for reading from memory (RAM) checks the cache for the data at the same time.

This is over simplifying it, but each block in the cache stores a memory address and a value. The CPU basically shouts, does anyone have memory address #52352, and all the cache blocks check themself, and if they do have it, they send it back.

The memory controller on the other hand, translates the memory address into a specific block of the RAM and requests the data stored there.

Ok, but how do the blocks of cache talk to the CPU? Is it still the same memory controller as main memory?

 

[imported_Seer]

There is probably an on die cache memory controller. It would likely be simplistic. Maybe not though; the MC might have integrated prefetching functions and stuff like that, I just don't know. But there has to be some sort of way for the CPU to access cache, and going off to the northbridge would be silly (so would using what would probably be a higher latency on die MC in the case of AMD). Doing so would eliminate the benefit of cache over RAM.

 

[Born2bwire]

Don't know about in actual industry implementation, but when I did it, the memory ops from the CPU just went directly to the cache. If the cache has a miss then it started sending the necessary control signals up the chain to the L2->RAM->etc. I would imagine it is more or less what they would actually do in practice since you want to grab the data from the cache as fast as possible, that is, check the cache first and if you have a miss then move up to the memory controller (unless it is efficient to start them both off in parallel).

 

[imported_Tick]

Originally posted by: Born2bwire
Don't know about in actual industry implementation, but when I did it, the memory ops from the CPU just went directly to the cache. If the cache has a miss then it started sending the necessary control signals up the chain to the L2->RAM->etc. I would imagine it is more or less what they would actually do in practice since you want to grab the data from the cache as fast as possible, that is, check the cache first and if you have a miss then move up to the memory controller (unless it is efficient to start them both off in parallel).

Oh, so you just had the CPU output memory ops directly, and it just pulled the correct data from cache without any intermediate memory controller? Huh. I didn't know CPU's put out memory ops directly.

 

[Born2bwire]

Originally posted by: Tick

Originally posted by: Born2bwire
Don't know about in actual industry implementation, but when I did it, the memory ops from the CPU just went directly to the cache. If the cache has a miss then it started sending the necessary control signals up the chain to the L2->RAM->etc. I would imagine it is more or less what they would actually do in practice since you want to grab the data from the cache as fast as possible, that is, check the cache first and if you have a miss then move up to the memory controller (unless it is efficient to start them both off in parallel).

Oh, so you just had the CPU output memory ops directly, and it just pulled the correct data from cache without any intermediate memory controller? Huh. I didn't know CPU's put out memory ops directly.

Well the microinstructions give memory addresses for the data or instructions. So when it needs to read or write data, it just sends the appropriate data signals and address to the memory, which is purely a black box to the CPU.

 

[alpha88]

There really isn't a memory controller for the cache in the same way that there is for RAM. The memory controller determines which area of memory to read data from (based upon the address). This is why it is possible to have gigs of ram.

This doesn't happen with the cache, every single block is accesed at the same essentially, but only if one of them contains the correct data is it used (otherwise the main memory is accessed). This is why it is difficult to have lots of cache (and they take up space). In general, to add more cache, they need to add more steps to the process, which makes it run slower, so you get multiple levels of cache.