Some questions about the Hammer Integrated memory controller

[YossI]

Its My first post here so I dunnu if this belongs in highly technical? (we don't have forums of this level in Israel?).

How can I generally think of FSB on the hammer? Is the hammer memory controller capable of accessing the memory for each CPU clock cycle??
Will the hammer require any modification in order to work with higher then PC2700 memory models? Or is the fact that the memory controller is integrated on the chip it self gives Chip-set manufactures the ability to combine any type of memory at any speed with the Hammer? should we expect this to take place?

Thank you very much?
🙂😛

 

[CTho9305]

interesting question... I wonder how well the hammer mem controller overclocks 😉

 

[Burnsy]

From the Anandtech article on the technology behind the Hammer:



<< Thus the Hammer architecture calls for an integrated memory controller (MCT) and an integrated DRAM controller (DCT). The memory controller is a generic interface between the Hammer core itself and the DCT; this controller understands what memory is but isn't tied down to a particular type of memory. The MCT interfaces with the DCT which is much more specific and deals with specific types of memory. AMD could theoretically produce a Hammer with DDR SDRAM support and another with RDRAM support just by changing the DCT >>

 

[Mday]

one comment only

FSB has been, and always will be, for now, the measure of the frequency at which the PROCESSOR and the CORE LOGIC chipset of the motherboard communicate.

 

[YossI]

<< From the Anandtech article on the technology behind the Hammer:



<< Thus the Hammer architecture calls for an integrated memory controller (MCT) and an integrated DRAM controller (DCT). The memory controller is a generic interface between the Hammer core itself and the DCT; this controller understands what memory is but isn't tied down to a particular type of memory. The MCT interfaces with the DCT which is much more specific and deals with specific types of memory. AMD could theoretically produce a Hammer with DDR SDRAM support and another with RDRAM support just by changing the DCT >>

>>



ok, thnx.
so from what i understand in-order to work with other memory-interfaces (like RDRAM narrow memory interface) the DCT unit will have
to be modified... BUT do this apply to faster DDR-SDRAM or other memory types sharing DDR-SDRAM memory interface (QDR? QBM?) ?
how limiting is the on_die DRAM controller?

maybe this is yet to be answered by anyone...?

thnx, YossI

 

[Locutus4657]

Yes, to make hammers officially compatible with newer types of memory AMD will have to make modifications to the hammer chip it's self. Which means if you want faster memory you have to buy a new CPU and potentially a new MB (though not neccesarly a new MB). I can't wait till AMD's hammer is out, I want one!

Carlo



<<

<< From the Anandtech article on the technology behind the Hammer:



<< Thus the Hammer architecture calls for an integrated memory controller (MCT) and an integrated DRAM controller (DCT). The memory controller is a generic interface between the Hammer core itself and the DCT; this controller understands what memory is but isn't tied down to a particular type of memory. The MCT interfaces with the DCT which is much more specific and deals with specific types of memory. AMD could theoretically produce a Hammer with DDR SDRAM support and another with RDRAM support just by changing the DCT >>

>>



ok, thnx.
so from what i understand in-order to work with other memory-interfaces (like RDRAM narrow memory interface) the DCT unit will have
to be modified... BUT do this apply to faster DDR-SDRAM or other memory types sharing DDR-SDRAM memory interface (QDR? QBM?) ?
how limiting is the on_die DRAM controller?

maybe this is yet to be answered by anyone...?

thnx, YossI >>

 

[AGodspeed]

I posted a response this exact same question in the thread you created here. I'll post it again. 🙂

<<<<

Good questions Yoss1. 🙂

How can I generally think of FSB on the hammer? Is the hammer memory controller capable of accessing the memory for each CPU clock cycle??

AMD's Hammer processors won't be released for at least another year, and so the frequency of the Hammer's FSB (and CPU speed) is still relatively unknown. However, Anand himself revealed several months back that Hammer might debut with an 800MHz FSB.

The Hammer's integrated Northbridge (with an onboard memory controller) allows for better direct access to main memory and therefore lower latency. Higher FSB frequencies occur as a result.

Will the hammer require any modification in order to work with higher then PC2700 memory models? Or is the fact that the memory controller is integrated on the chip it self gives Chip-set manufactures the ability to combine any type of memory at any speed with the Hammer? should we expect this to take place?

The Hammer's onboard memory controller will support PC2100 and PC2700 memory (and higher memory depending on the state of the market place).

For a much more indepth explanation of all of your questions, see AMD's Hammer FAQ (for some reason, AMD's Hammer PDF isn't functioning). >>>>