Discussion So what do you guys think of MIPS Open?

[whm1974]

Well the MIPS ISA has been opened up under a BSD style license:
https://www.mips.com/mipsopen/
Longer article:
https://www.electronicdesign.com/embedded-revolution/what-opening-mips-architecture-could-mean

Only MIPS version 6 has been made opened by Wave Technologies along with PowerVR. They basically doing this due to having lost major market share to ARM and that RISC-V has gain a large following and that many startups are using it.

One advantage the MIPS Open has over RISC-V is maturity as MIPS has been long established and proven to work and hardware is available. I will consider this as useful as both a stopgap and as a backup in case RISC-V falls flat. Of course this will also give end-users another option to choose the best solutions.

I do see both RISC-V and MIPS Open co-existing among FOSS users, but what are you thoughts on this?

 

[whm1974]

Sorry I was mistaken about PowerVR, oops.

 

[NTMBK]

On the one hand, more diversity is good... On the other hand, it does run the risk of splitting attention between two competing free ISAs, to the detriment of both.

I suspect we'll see lots of embedded widgets built with free MIPS cores. We'll have to wait and see if it takes off anywhere else. I could see the likes of Google using it internally, as a host CPU for their Deep Learning hardware.

 

[whm1974]

On the one hand, more diversity is good... On the other hand, it does run the risk of splitting attention between two competing free ISAs, to the detriment of both.

I suspect we'll see lots of embedded widgets built with free MIPS cores. We'll have to wait and see if it takes off anywhere else. I could see the likes of Google using it internally, as a host CPU for their Deep Learning hardware.

Well I do see current MIPS users using MIPS Open, with the rest of Open Hardware being RISC-V based. In any case this should an exciting year for Open Source users.

I am now wondering if FOSS users will have heated debates on which ISA is better?

 

[DrMrLordX]

MIPS has already been effectively-open for awhile. Godson/Loongson are MIPS64 designs from ITC that only semi-recently (2011) received official licenses from MIPS. MIPS overlooked a fair amount of IP abuse from 2007-2011.

I don't know how many Loongson CPUs will be released in the future, but there's probably a fairly large base of the things still kicking around in China being slow. And stuff.

Point being, ITC demonstrated that people could trample MIPS IP in certain markets without and any significant consequences. Opening up their IP was probably the smart thing to do if they want to continue to cultivate MIPs in China where it has an installed base (sort of).

 

[whm1974]

MIPS has already been effectively-open for awhile. Godson/Loongson are MIPS64 designs from ITC that only semi-recently (2011) received official licenses from MIPS. MIPS overlooked a fair amount of IP abuse from 2007-2011.

I don't know how many Loongson CPUs will be released in the future, but there's probably a fairly large base of the things still kicking around in China being slow. And stuff.

Point being, ITC demonstrated that people could trample MIPS IP in certain markets without and significant consequences. Opening up their IP was probably the smart thing to do if they want to continue to cultivate MIPs in China where it has an installed base (sort of).

Well I already know about the Godson/Loongson from China, but I was under the impression that development has somewhat slowed down.

And I'm aware the RMS has been using a notebook using those CPUs/SOCs for awhile now, but I don't know if he is still using it.

With an already installed base, I will imagine that China will stick with what they have spent a large amount of money on developing. But from I know it is hard to get Loongson based hardware in the US, and likely to be expensive as well.

 

[DrMrLordX]

Yeah I think Loongson is mostly dead. They do not appear to have gotten to anything below 28nm, and not in great quantity. Someone might keep iterating upon the design, but it looks like companies like Huawei are leading the way with ARM instead.

 

[whm1974]

Yeah I think Loongson is mostly dead. They do not appear to have gotten to anything below 28nm, and not in great quantity. Someone might keep iterating upon the design, but it looks like companies like Huawei are leading the way with ARM instead.

I would think that with all that money and effort spent on reverse engineering and development, that they will continue further with improving and modernizing Loongson, and making systems using it more widely available.

 

[SarahKerrigan]

NanoMIPS is really well-designed as a compact ISA. Additionally, there are high-performance cores licensable from MIPS (I assume with physical IP), which is still something of a gap in RISC-V land.

I have real qualms about RISC-V at the ISA level (lack of pre- and post-increment being a big one) and the ecosystem is still pretty limited. MIPS Open is a good, good thing - the ISA has historically kind of sucked, but the introduction of NanoMIPS, and the addition of compact branches and SPR-less multiplies to the main ISA in R6, make it a heck of a lot more compelling. It also has a good DSP-type extension, while RV, last I looked, still has no standardized extension for packed SIMD and saturating arithmetic. (Dedicated multi-pipe vector hardware, like the RV guys seem to be in love with, is well and good for HPC but generally requires an additional register file; being able to do paired-element SIMD ops on GPRs is a very convenient thing.)

I think this creates a really large question of "why bother?" with RV - although it may be too little, too late, now that RV has acquired momentum.

 

[whm1974]

NanoMIPS is really well-designed as a compact ISA. Additionally, there are high-performance cores licensable from MIPS (I assume with physical IP), which is still something of a gap in RISC-V land.

I have real qualms about RISC-V at the ISA level (lack of pre- and post-increment being a big one) and the ecosystem is still pretty limited. MIPS Open is a good, good thing - the ISA has historically kind of sucked, but the introduction of NanoMIPS, and the addition of compact branches and SPR-less multiplies to the main ISA in R6, make it a heck of a lot more compelling. It also has a good DSP-type extension, while RV, last I looked, still has no standardized extension for packed SIMD and saturating arithmetic. (Dedicated multi-pipe vector hardware, like the RV guys seem to be in love with, is well and good for HPC but generally requires an additional register file; being able to do paired-element SIMD ops on GPRs is a very convenient thing.)

I think this creates a really large question of "why bother?" with RV - although it may be too little, too late, now that RV has acquired momentum.

When we started developing RISC-V in 2010, we decided against adopting the OpenRISC ISA for several technical reasons:

OpenRISC had condition codes and branch delay slots, which complicate higher performance implementations.
OpenRISC uses a fixed 32-bit encoding and 16-bit immediates, which precludes a denser instruction encoding and limits space for later expansion of the ISA. This pretty much entirely eliminates the ability to explore new research architectures.
OpenRISC does not support the 2008 revision to the IEEE 754 floating-point standard.
There was no 64-bit address space version of OpenRISC when we began. While there has been some work since 2010 towards the 64-bit address space version of OpenRISC, hardware implementations and software stacks are still not available.

Many of the above reasons also apply to MIPS, but with the added legacy and patent and trademark issues.

By starting from a clean slate, we could design an ISA that met all of our goals.
https://riscv.org/faq/
Other documents go in more detail.

 

[SarahKerrigan]

When we started developing RISC-V in 2010, we decided against adopting the OpenRISC ISA for several technical reasons:

OpenRISC had condition codes and branch delay slots, which complicate higher performance implementations.

Delayed branches are deprecated in MIPS R6, as I already mentioned, and I don't think they ever existed in nanoMIPS.

OpenRISC uses a fixed 32-bit encoding and 16-bit immediates, which precludes a denser instruction encoding and limits space for later expansion of the ISA. This pretty much entirely eliminates the ability to explore new research architectures.

That's a hell of an excuse for RV's undersized immediate ranges.

OpenRISC does not support the 2008 revision to the IEEE 754 floating-point standard.

MIPS R6 had modifications to support IEEE 754-2008, per my recollection.

There was no 64-bit address space version of OpenRISC when we began. While there has been some work since 2010 towards the 64-bit address space version of OpenRISC, hardware implementations and software stacks are still not available.

Unlike OpenRISC, MIPS has had 64-bit implementations since the early 1990s.

Many of the above reasons also apply to MIPS, but with the added legacy and patent and trademark issues.

Depending on the terms of OpenMIPS, this looks like it's about to become a moot point.

 

[whm1974]

Well personally I do think that there will be room for both open ISAs as folks will simply choose which one best fits their needs based on availability.

Some vendors may even use both.

 

[SarahKerrigan]

Well personally I do think that there will be room for both open ISAs as folks will simply choose which one best fits their needs based on availability.

Some vendors may even use both.

That's probably true. Andes and Cortus are probably big enough players to ensure RV won't simply fade away - although Andes, at least, has felt the need to substantially extend the ISA.

IMO whether Open MIPS gets that kind of momentum depends at least partially on whether free cores emerge.

 

[whm1974]

That's probably true. Andes and Cortus are probably big enough players to ensure RV won't simply fade away - although Andes, at least, has felt the need to substantially extend the ISA.

IMO whether Open MIPS gets that kind of momentum depends at least partially on whether free cores emerge.

With both RISC-V and MIPS Open being available, I'm wondering what the next three to five years will bring? Although I expect that the first consumer/prosumer type products will be geared towards hobbyist and maker usages, such as lower cost SBCs.

Hmm, are the guys that are heavily invested in the ARM ecosystem outright panicing over two ISAs being Open specs at the moment?

 

[Nothingness]

MIPS was the first RISC ISA I used back when Digital were doing workstations with them in 1990. I wrote a compiler back-end for it. Some years later I got back to MIPS with Linux for Playstation 2. MIPS had become a horrible mess of non compatible variants of the instruction set and I had to backport proprietary changes to binutils/gcc into more recent version of the tools. What a horrible pain! Since that time I felt that MIPS was doomed or at least something I would never work with anymore.

And RISC-V looks the same to me. Being too open can lead to fragmentation. Time will tell how things go but I would not work on it yet. If I still was in the University I would choose RISC-V.

That's the point of view of someone heavily invested in the ARM ecosystem. But also the point of view of someone who complains that Intel doesn't have the same ISA everywhere (AVX not available on all CPU), or that ARM and Nvidia were stupid enough to have a CPU without NEON.

 

[whm1974]

@Nothingness From watching these videos from RISC-V it does looks like that both the RISC-V Foundation and vendors are taking very hard efforts and a great deal of it from the start to prevent fragmentation.

From what I have been watching, you can already build a basic PC using the SiFive Freedom Unleashed SBCs with the expansion board and a video card. Running Debian. However it is quite expensive right now to do.
https://www.youtube.com/channel/UC5gLmcFuvdGbajs4VL-WU3g

Edit: added the videos I forgot

 

[Nothingness]

I guess you are aware the first of these videos was sponsored by SiFive. That makes me cautious about any claim made in it.

Anyway I hope you are correct and that fragmentation will be limited. New players always is a good thing for competition.

But again being open is not enough to guarantee anything. For instance people don't care if Linux is open. Can it run what they need? For many of them no, so they use Windows. Don't get me wrong, I almost exclusively use Linux, but that's because I was using UNIX before Windows 3 even existed, not because it's open.

Out of curiosity, what good does it do to you as an end user that RISC-V is open?

 

[SarahKerrigan]

@Nothingness From watching these videos from RISC-V it does looks like that both the RISC-V Foundation and vendors are taking very hard efforts and a great deal of it from the start to prevent fragmentation.

From what I have been watching, you can already build a basic PC using the SiFive Freedom Unleashed SBCs with the expansion board and a video card. Running Debian. However it is quite expensive right now to do.
https://www.youtube.com/channel/UC5gLmcFuvdGbajs4VL-WU3g

Edit: added the videos I forgot

Are you looking for technical discussion, or are you just here to advertise RISC-V at us?

"Leaving basic stuff out of the ISA, and then telling vendors to go have fun with extensions" must be a new and unintuitive definition of "preventing fragmentation" that I was previously unaware of.

 

[whm1974]

I guess you are aware the first of these videos was sponsored by SiFive. That makes me cautious about any claim made in it.

Anyway I hope you are correct and that fragmentation will be limited. New players always is a good thing for competition.

But again being open is not enough to guarantee anything. For instance people don't care if Linux is open. Can it run what they need? For many of them no, so they use Windows. Don't get me wrong, I almost exclusively use Linux, but that's because I was using UNIX before Windows 3 even existed, not because it's open.

Out of curiosity, what good does it do to you as an end user that RISC-V is open?

Right now? Well the truth is not much, but it could ensure that Personal Computering doen't become Closed, Walled Garden, and Locked Down.

 

[whm1974]

Are you looking for technical discussion, or are you just here to advertise RISC-V at us?

"Leaving basic stuff out of the ISA, and then telling vendors to go have fun with extensions" must be a new and unintuitive definition of "preventing fragmentation" that I was previously unaware of.

A technical discussion, as what would be the point of me advertising something that I'm not "invested in"? If I am unwitting Hyping RISC-V please feel free to bring me back to Reality.

And yes I'm well aware that SiFive sponsored the videos.

 

[SarahKerrigan]

A technical discussion, as what would be the point of me advertising something that I'm not "invested in"? If I am unwitting Hyping RISC-V please feel free to bring me back to Reality.

And yes I'm well aware that SiFive sponsored the videos.

Whenever me or anyone else criticizes RV in concept or implementation, you just reply with "yeah, but the RV foundation says no."

Do you think the limited immediate range, lack of pre- or post-increment addressing modes, lack of embedded-oriented SIMD, and current selection of cores are good or bad? Why or why not? What makes RV better (or worse) than SPARC or MIPS, one of which is open and the other of which will be soon? How about vs ARM, which is not open but is the de facto standard in low-power 64-bit, and the dominant player in 32-bit as well?

 

[whm1974]

Whenever me or anyone else criticizes RV in concept or implementation, you just reply with "yeah, but the RV foundation says no."

Do you think the limited immediate range, lack of pre- or post-increment addressing modes, lack of embedded-oriented SIMD, and current selection of cores are good or bad? Why or why not? What makes RV better (or worse) than SPARC or MIPS, one of which is open and the other of which will be soon? How about vs ARM64, which is not open but is the de facto standard in low-power 64-bit, and the dominant player in 32-bit as well?

Well to be fair I really don't know much about CPU design to commit on the merits of various ISAs, i just have have more information about RISC-V ATM. MIPS Open just started, and I will need to look into OpenSPARC as well(will do).

I will try to learn about other Open ISAs so I will have unbiased view as much as possible.

 

[teejee]

Whenever me or anyone else criticizes RV in concept or implementation, you just reply with "yeah, but the RV foundation says no."

Do you think the limited immediate range, lack of pre- or post-increment addressing modes, lack of embedded-oriented SIMD, and current selection of cores are good or bad? Why or why not? What makes RV better (or worse) than SPARC or MIPS, one of which is open and the other of which will be soon? How about vs ARM, which is not open but is the de facto standard in low-power 64-bit, and the dominant player in 32-bit as well?

Of course you're free to criticize RV. But the design goal of RV is to have a small and simple base ISA.
A 400MHz RV core could very well be faster, cheaper and have same power draw as a more complex ISA at 300Mhz at same process (figures just for explanation). So losing a few % here and there due to simple ISA could still give you the best overall product. High end server, desktop and smartphone is another thing though, at those clocks the power draw increases very fast with increases frequency.

And the current momentum behind RV and power efficiency of some RV CPU's indicates that this design choice is appreciated by many.


Here is a recent article in eWEEK:
https://www.eweek.com/pc-hardware/six-trends-experts-see-for-advancement-of-risc-v-in-2019

 

[Nothingness]

Here is a recent article in eWEEK:
https://www.eweek.com/pc-hardware/six-trends-experts-see-for-advancement-of-risc-v-in-2019

This is typical of the silly marketing that goes around RISC-V. Did you check who made the quotes cited in that "article"? 4 from Naveed Sherwani, CEO of SiFive, Martin Fink CTO of WD (early adopter who has a vested interest in seeing RISC-V not fail) and Rick O'Connor member of the RISC-V foundation. Would you really trust these people to have an unbiased view of RISC-V?

 

[Hi-Fi Man]

Don't forget about POWER. If you want a truly open system check out https://www.raptorcs.com/. The developer of TenFourFox (for PowerPC Macs) also has an interesting little site about these systems and running them; https://www.talospace.com/.