Sledgehammer samples next month !!!

[Czar]

http://www.theregister.co.uk/content/1/12119.html


<< Sources close to AMD have reported that first silicon is expected for its 64-bit microprocessor, codenamed Sledgehammer, as early as next month.

That news is likely to horrify Intel executives who were forced to admit last week that delivery of its Itanium processor slipped a quarter, due to unspecified difficulties.

One source said that AMD's &quot;lightning data transport&quot; (LDT) is the real key to the performance advantages expected when silicon samples ship.

AMD's 64-bit processor, which maybe should be codenamed Iceberg if Intel's chip does turn out to be the Itanic, will not require massive operating system and application software porting exercises.

According to rumours, and we stress there is no hard evidence for this as yet, within the community of chip architects in Silicon Valley last week, Intel is readying an alternative 64-bit platform in case it is forced by circumstances to follow AMD's strategy.

That work may be carried out by the group of Intel architects in Oregon who worked on the Willamette platform. As we have reported here previously, there is little love lost between that team and the Santa Clara based team which developed the Merced-Itanium platform.

One chip architect working for a third party firm said that if Intel decided to take this action, it resembled the i432 project the firm canned in 1978, which it replaced with the 8086 microprocessor. Two engineers at Intel managed to cobble together the 8086 in a mere three weeks. The rest is history... >>

 

[Goi]

Wow, that's great news, but we still have no concrete specs of the Sledgehammer though...

 

[Czar]

We know it is basicly a x86 processor with added 32 instructions. So it will be a next step like going from 16bit 486 to 32bit Pentium.

Itanium is based on new instruction sets so its new, no next step from soemthing else, meaining Intel has to get alot of support.

 

[KarsinTheHutt]

Intel traditionaly garners much support, simply because it is intel. But on the other hand, Intel provides compilers that optimize code for its chips, making it easier for developers to take advantage of new architectures/instruction sets.

As I recall, M$ demonstrated 64 bit windows 2000 at the dotNet forum two weeks ago. And IA-64 linux (aka Trillium) is almost done.

Anyhow... I'm wondering how much longer AMD can keep increasing x87 FPU performance. The Athlon is great - but it has a HUGE amount of transistors. There has to be a better way to increase performance.

 

[jpprod]

Personally I suspect SledgeHammer to be an Athlon deriative with 64bit extensions, two cores on single die connected with LTD bus and an large unified ondie L2 cache for these cores. Athlon core has many similarities with 64bit Alpha, I guess that's one of the reasons why AMD scrapped K8 in favour of SledgeHammer (other being resignation of a key K8 designer back then, of course).

 

[apoppin]

Want a detailed explanation of the Sledgehammer?

http://www.realworldtech.com/page.cfm?articleid=RWT071800000000

 

[Noriaki]

We know it is basicly a x86 processor with added 32 instructions. So it will be a next step like going from 16bit 486 to 32bit Pentium.

Well you're half right. Your only problem is that the 486 is a 32bit CPU, it just didn't have a mainstream 32bit OS to take advantage of it. Even the 386 was 32bit.

[edit] Sorry about the pickiness I just woke up and I'm a grump in the morning [/edit]

But you are right in principle, the sledgehammer is just another extentsion of the x86 ISA, it started out at 8 bit in the 8088 (well technically that was not an x86, but ) then moved up to 16 bit in the 8086, 80186 (yes there was one), 80286, then to 32bit in the 80386, 80486 and anything newer. Finally we have yet another extension to this venerable ISA to 64bit in the K8.

 

[Goi]

Thanks for the link, apoppin

 

[Sunner]

jp, you're absolutely correct, the Sledgehammer is a much enhanced 64 bit K7.
Aside from x86-64 it has support for CMP as well, like you said.
Have a look-see at Paul DeMone's article on http://www.realworldtech.com, very informative, especially the info on the new fpu model.

 

[JCholewa]

Czar: As mentioned before, the 80486 is a 32-bit architecture. So is, I recall, the 80386.

It goes like this:
8086: 8-bit
8088: 8/16-bit (???)
80286: 16-bit
80386SX: 16/32-bit
80386SX + 80387: 16/32-bit, off-die fpu
80386DX: 32-bit
80386DX + 80387: 32-bit, off-die fpu
80486SX: 32-bit, pipelined, on-die cache
80486DX: 32-bit, pipelined, on-die cache, on-die fpu
80486SX + 80487: 32-bit, pipelined, on-die cache, off-die fpu
P5: 32-bit, Superscalar, pipelined, on-die cache, on-die fpu, pipelined fpu
6x86: 32-bit, Superscalar, pipelined, on-die cache, on-die fpu
K5: 32-bit, [very] Superscalar, pipelined, on-die cache, on-die fpu, pipelined fpu
P55c: Same as P5, but with more cache and int SIMD
PPro/PII: 32-bit, Superscalar, superpipelined, on-die cache, on-die fpu, pipelined fpu, OoO execution
6x86MX/MII: Same as 6x86, but with more cache and int SIMD
K6: 32-bit, Superscalar, pipelined, on-die cache, on-die fpu, int SIMD
K6-2: 32-bit, Superscalar, pipelined, on-die cache, on-die fpu, int SIMD, pipelined fp SIMD, superscalar sp (single precision) fp SIMD, prefetching
Mendocino/Celeron: 32-bit, Superscalar, superpipelined, on-die cache, on-die fpu, pipelined fpu, OoO execution, on-die multilevel cache
Katmai/PIII: 32-bit, Same as PPro/PII, but with sp fp SIMD
K6-III: Same as K6-2, but with on-die multilevel cache
K7/Athlon: 32-bit, Superscalar, superpipelined, on-die cache, on-die fpu, pipelined fpu, superscalar fpu, OoO execution, pipelined sp fp SIMD, superscalar fp SIMD, prefetching
Coppermine/PIII: 32-bit, Superscalar, superpipelined, on-die multilevel cache, on-die fpu, pipelined fpu, OoO execution, sp fp SIMD, prefetching, on-die multilevel cache
&quot;Thunderbird&quot; K7/Athlon: 32-bit, Superscalar, superpipelined, on-die multilevel cache, on-die fpu, pipelined fpu, superscalar fpu, OoO execution, pipelined sp fp SIMD, superscalar sp fp SIMD, prefetching
Willamette/P4: 32-bit, Superscalar, superpipelined, on-die multilevel cache, on-die fpu, pipelined fpu, OoO execution, full (double and single precision) fp SIMD, prefetching, on-die multilevel cache, on-die trace cache
K8/Sledgehammer: 64-bit, Superscalar, superpipelined, on-die multilevel cache, on-die fpu, pipelined fpu, superscalar fpu, OoO execution, pipelined sp (maybe full) fp SIMD, superscalar sp (maybe full) fp SIMD, prefetching, superscalar/pipelined TFP (three-operand, flat register fpu), maybe three-operand fp SIMD, CMP (on-die multiprocessing) support


Okay ... I may have messed up a little on the details, but perhaps this can be used as a general guideline.

The K8 completely revamps the floating point capability of x86 and makes it a lot faster. K8 increases the memory addressability of the x86 architecture and allows for work to be done on 64-bit integer and GP registers directly instead of in some half-assed SIMD manner. It's *possible* that K8 will support three-operand, flat register double and single precision floating point SIMD, but no guarantee on that. Lastly, K8 adds CMP support, which is the ability to put more than one processor onto a single cpu die (this is a *huge* thing).

Not counting CMP, the jump from Thunderbird/Athlon to Sledgehammer seems to me roughly equivalent to the jump from 80286 to 80386DX + 80387. CMP is really a nice addition, so I'd say that the K8 hop is somewhat greater than the above-mentioned comparison.

Of course, any surprised other than this, like a deeper instruction pipe or more superscalarness (dah, comrade, even more load-store units!), would kind of just be more than we can realistically ask for and would personally make my jaw drop (metaphorically) to the other side of the planet.

-JC
PC News'n'Links
http://www.jc-news.com/pc

PS: Please correct me if I made any mistakes on those processor core rundowns, they were very hastily thrown together, and please be nice and do not flame me.

 

[ragiepew]

whhheeeewwww.. damn nice post JC...

 

[Czar]

JCholewa

Very very nice post

Just I forgot myself a bit, it wasnt untill the year of Pentium that I realy got into hardware so I wasnt sure about how the older cpus were. Sortof a lost memmory.


btw. very nice to see you on this forum

 

[jpprod]

JC, a very long time ago I recall reading, that i80486SX was actually the same CPU as i80486DX, but it had the on-die FPU disabled by Intel, and that i80487 included FPU as well as the i80486 integer ALU. This way i80486SX + i80487 could match the i80486DX in performance. According to the article, it was also why i80487 was so damn expensive. Kinda silly when you think about it, but could be true if the FPU was the part keeping i80486DX CPUs from ramping MHZ-wise.

Then again, it's years since I read the article. Also, I can't remember whether it was April 1st back then, so by all means, take this with a grain of salt

 

[MadRat]

They should just take the FPU off the processor and build a bridge to a dedicated FPU unit! Would make lots more sense - buy only what level of performance you need. Personally I use alot of integer intensive programs and could care less the FPU.

 

[JCholewa]

madrat: I prefer modular designs like that, too. But it is important to note that you get a performance boost by moving the fpu onto the die. Although latencies are not as important with floating point units as they are with caches, a doubling or tripling of the instruction latencies (from 4 to 12 cycles for an FADD, perhaps?) could really hurt performance in some cases, I'd imagine.

Still ... woulda been nice to buy a cheapo K6-2+, then tack on a K7 fpu and overclock the fpu only... <g>

-JC

 

[Sunner]

Jp, Ive heard that too, also heard that the name &quot;sx&quot; is short for &quot;Sux&quot;
Dont know if its true, but you never know

 

[Dragon Puppy]

JCholewa:

I remember it more like this

80286 no SX or DX model
80287 co-FPU optional

80386SX without FPU
80386DX with on-die FPU
80387 optional Co-FPU unit for SX

I had a 386SX 16MHz while my friend had an 286 16MHz with an 287(12MHz?) FPU and his FPU score in checkit was much higher than mine. If I remember correctly he changed it(287)to an AMD FPU and it was faster!! so even then AMD FPU ruled!

 

[JCholewa]

Dragpup: I can say with almost 100% certainty that the 386SX was not a 386 sans fpu. To my knowledge, the 486 was the first x86 processor to integrate in fpu onto the processor die.

http://einstein.et.tudelft.nl/~offerman/cl.2.25.2.html -- 80386SX
&quot;32 bit internal data bus.
16 bit external data bus (SX: Single-word eXternal).
24 bit address bus.&quot;

http://einstein.et.tudelft.nl/~offerman/cl.2.25.1.html -- 80386DX
&quot;32 bit internal data bus.
32 bit external data bus (DX: Double-word eXternal).
32 bit address bus.&quot;

Also, http://einstein.et.tudelft.nl/~offerman/cl.2.32.1.html (80486DX) mentions specifically &quot;Build-in FPU (Floating Point Unit)&quot; whereas none of the 80386 entries say so.


jpp: I do not remember who told me this, but a very technically oriented person (possibly an Intel employee) informed me at one point that only 80486SX engineering samples used the 80486DX core with the x87 disabled. All actual production models had no actual x87 (fpu) on the die, and you can verify that by comparing the die sizes of an 80486DX and an 80486SX.

-JC
PC News'n'Links
http://www.jc-news.com/pc

 

[Czar]

The difference between 486sx and 486dx was the missing math co processors which did FPU calculations. Same goes for 386sx and dx.
The Overdrive processors for sx was basicly then just a math coprocessor.


This is sooo weird, the thread started with news about the new 64bit Sledgehammer and now we are talking about 386 and 486

 

[JCholewa]

Cz: Unfortunately, we seem to be in total disagreement regarding the 80386SX. Could you please post a source backing up your assertion? Thanks.

-JC

 

[CQuinn]

JCholewa:
Wonderful post, thank you. This makes me look forward to
seeing reviewers of the Sledgehammer even more (I doubt I'll
be able to afford one though).

To address the (???) at the beginning of your list (IIRC):

8088: 8 bit register/8-bit bus
8086: 8 bit register/16-bit bus.

==
jpprod:

I think the earlier 80486SX CPUs were 80486s with the FPU disabled
(sold to compete with the faster AMD 80386-clones), but later
when Intel saw there was money in the low end of the market, they
redesigned an 80486 core without an FPU.

At the time this was not a bad idea, as most of the popular apps
were still integer based, and there were fewer power-users that
demanded FPU support.

I agree though, it was widely considered a scam (at first) on Intels part that the 80487 &quot;FPU chip&quot; was really a 486DX in disguise.
They sort of made up for that by adopting the internal clock
multiplier for the CPUs (first started by AMD?) that we all
know and love today.

 

[Czar]

JC, well actually I cant back that 100% up, because I only have it in some old computer magazines at home and I´m only talking from memmory.

But it was something like this, when I was having fun with Povray on my old 20mhz 386sx then it wouldnt run because it needed a math co processor, aka DX system. I had a little program that would emulate the coprocessor, it did work, I think had the computer running for about 30hrs and just about 1% had been finished.

 

[Dragon Puppy]

Atleast my IBM PS/1 (=Crap of Computer) had a 386 CPU wich was really small around 20x20mm, and a old server that I resently pulled apart that had an 386DX processor and it's much bigger 40x40mm , so I thought it had the FPU on-die.

 

[dszd0g]

Yeah, nice general JC. Dragon Puppy's and CQuinn's corrections are how I remember things.

As I recall (this was a long time ago), the 8088 came out before the 8086. If I remember things correctly, Intel developed the 8086 first but they thought it would be too expensive and in order to cut costs released the 8088. Take this with a grain of salt though.

 

[pm]

JC's right about the difference between the 386SX and 386DX. The first x86 CPU with a built-in floating point unit was the 486. I can back up my assertion (that's he right) with several paper articles.

Good to see you around these parts, JC.

Patrick Mahoney
IA64 Microprocessor Design
Intel Corp.