Skylake-EP to have FIVR

[Arachnotronic]

Synthesis, APR and Section Timing Owner (Skylake Server – 14nm Xeon CPU) : January 2013 - March 2015
• RLS design block ownership in on-die FIVR (Fully Integrated Voltage Regulator).
• Owned timing and layout convergence of the brand new design block in FIVR with multiple clocks, resolved additional challenges as the block was a MI (Multiple Instances) fub (design block) in sections with section specific critical path timing and multi clock domains.
• Section Timing Owner (STO) for FIVR: responsible for section timing convergence, debugged and drove convergence for layout and PV quality for multiple FIVR sections, coordinated with multiple design block owners to help them converge their designs, diligently managed section rollups to fullchip models with all quality checks while driving issues with external design section stakeholders.
• Successfully managed additional challenges due to multiple FIVR sections having many unique violations due to unique clocking structure, large number of voltage sources and analog signals.

https://www.linkedin.com/profile/vi...argetId:10800028,VSRPcmpt:primary,VSRPnm:true

Also looks like the design is basically done since the engineer has moved on to Cannonlake Server.

 

[ShintaiDK]

Icelake will also reintroduce it to the LGA11xx. So its already refined with Skylake-EP.

 

[iSkylaker]

Sorry for the off-topic, but what is Icelake I've seem few posters mentioning it and I can't find anything about it on the web. Sucessor of Cannonlake? any roadmap I'm missing?

 

[Arachnotronic]

Sorry for the off-topic, but what is Icelake I've seem few posters mentioning it and I can't find anything about it on the web. Sucessor of Cannonlake? any roadmap I'm missing?

I believe Icelake is the "tock" that comes after the Cannonlake "tick".

 

[iSkylaker]

I believe Icelake is the "tock" that comes after the Cannonlake "tick".

Gotcha, I looked on the web and can't find anything about it.

 

[ShintaiDK]

Skylake->Cannonlake->Icelake.

For desktop users its Skylake->Skylake Refresh->Icelake.

 

[IntelUser2000]

Icelake\Kabylake might be another tick based on 10nm chip from the naming.* There were pretty credible rumors that Intel was going to introduce a third chip after Sandy Bridge because of potential issues of 22nm but it worked out and we saw a 22nm part.

The fact that they almost had an issue so far back then suggests 10nm might be a longer living node than most. A Tock happens when the process is pretty mature.

*Sandy Bridge/Ivy Bridge
Haswell\Broadwell
Skylake/\CannonlakeIcelake?

What if only certain Skylake chips were supposed to have FIVR?

 

[RaistlinZ]

FIVR all through the night.

 

[PaulIntellini]

I think the current FIVR is better suited for servers than for fanless mobile.
- Package height is not an issue, so you have more space for the air core inductors
- Low load efficiency is not that important
- Package cost can be higher
- server has much more cores with bigger die, so per core voltage tweaking against intra-die variation is more important.
- FIVR reduces the number of pins (higher input current), Skylake Server already has a huge number of pins so that helps.

Here's a presentation from the "Cool Chips" conference that explains some of the issues the Broadwell team had to deal with to improve FIVR:
http://news.mynavi.jp/articles/2015/05/22/coolchips18_broadwell02/

 

[mrtastee]

Skylake-E will still be without FIVR, correct?

 

[ShintaiDK]

Skylake-E will still be without FIVR, correct?

Seems it will have FIVR.

The only reason FIVR was removed from Skylake was due to the tablet models and lack of time according to the Skylake lead designer.

In an interesting side note, Intel removed the integrated voltage regulator from the new SoC to hit tablet power consumption levels. “We didn’t have time to be flexible enough to have it in higher SKUs -- we were limited in time,” said Mandelblat.

 

[tenks]

Skylake->Cannonlake->Icelake.

For desktop users its Skylake->Skylake Refresh->Icelake.

You are more in the know than me, but from all the current official news it seems like canonlake still might make it to desktop. I didn't read it was canned, just pushed out, ie 10nm, which is why we're getting a 3rd 14nm chip in kabylake.

Skylake->Kabylake->Cannonlake->icelake

Weird, how we only got 2 bridges and 2 wells, but 4 lakes. LOL

 

[Idontcare]

You are more in the know than me, but from all the current official news it seems like canonlake still might make it to desktop. I didn't read it was canned, just pushed out, ie 10nm, which is why we're getting a 3rd 14nm chip in kabylake.

Skylake->Kabylake->Cannonlake->icelake

Weird, how we only got 2 bridges and 2 wells, but 4 lakes. LOL

Yep. No Skylake refresh, but Kabylake is a 14nm successor to Skylake and will precede 10nm Cannonlake. Nothing got cancelled, Kabylake got added and everything in the pipe after kabylake got pushed out 1 year because 10nm HOL is pretty bad.

 

[Arachnotronic]

Yep. No Skylake refresh, but Kabylake is a 14nm successor to Skylake and will precede 10nm Cannonlake. Nothing got cancelled, Kabylake got added and everything in the pipe after kabylake got pushed out 1 year because 10nm HOL is pretty bad.

Idontcare,

Iif 10nm yields are in the gutter right now leading to Kabylake, why doesn't Intel just skip Cannonlake (which won't bring too many improvements over Kabylake) and go to Icelake (10nm "tock") once yields there are good?

 

[PPB]

My next cpu, if from Intel, will sure have a FIVR, the benefits seen in Haswell were too hard to pass up, it basically made a lot more of motherboard choice for overclocking than before. Hopefully OEMs dont retain the power delivery gimping as seen in the transition from z87 to z97 and in the very latest motherboard revisions.

 

[Arachnotronic]

My next cpu, if from Intel, will sure have a FIVR, the benefits seen in Haswell were too hard to pass up, it basically made a lot more of motherboard choice for overclocking than before. Hopefully OEMs dont retain the power delivery gimping as seen in the transition from z87 to z97 and in the very latest motherboard revisions.

Don't worry, the FIVR is coming back. Skylake-E will have it and Icelake will most likely have it too.

 

[Idontcare]

Idontcare,

Iif 10nm yields are in the gutter right now leading to Kabylake, why doesn't Intel just skip Cannonlake (which won't bring too many improvements over Kabylake) and go to Icelake (10nm "tock") once yields there are good?

You still need that test vehicle for ramping the new node, that doesn't go away even with 10nm pushed out a year.

Think about driving your car to go to the grocery store. Just because you decide to procrastinate and go tomorrow instead of today doesn't mean you won't have to start your car whenever you finally decide to drive it.

Those ticks serve a purpose, that purpose doesn't go away even if the HVM ramp date for the node is delayed.

 

[witeken]

I believe Icelake is the "tock" that comes after the Cannonlake "tick".

Many lakes these days.

 

[witeken]

Idontcare,

Iif 10nm yields are in the gutter right now leading to Kabylake, why doesn't Intel just skip Cannonlake (which won't bring too many improvements over Kabylake) and go to Icelake (10nm "tock") once yields there are good?

Because Tick Tock. 10nm will be with us for 2 years, so 2 product lines. This will have least amount of problems and difficulty.

 

[NTMBK]

Because Tick Tock. 10nm will be with us for 2 years, so 2 product lines. This will have least amount of problems and difficulty.

At least 2 years...

 

[podspi]

I thought FIVR was supposed to increase energy efficiency? So why did they have to remove it for the most TDP-constrained products?

Or does it have to do with thermal density?

 

[NTMBK]

Interesting that Skylake-EP gets both AVX-512 and FIVR. I wonder if the two are connected? AVX2 already caused a big jump in power consumption, forcing clocks on Haswell-EX to drop down a bit compared to non-AVX code (by design). Doubling the throughput has to make it an even bigger hit. FIVR should make fine grained voltage control easier, in theory.

 

[stuff_me_good]

What are AVX benefits anyhow? I'm yet to see any.

 

[CHADBOGA]

I thought FIVR was supposed to increase energy efficiency? So why did they have to remove it for the most TDP-constrained products?

Or does it have to do with thermal density?

This is the question I would like answered too.

 

[Sweepr]

This is the question I would like answered too.

Answer here.