Skylake-EP (speculation)

[Ajay]

So, this is a bit out there, but I was just listening to the recent TR podcast after AMD's analyst day and something David Kanter said really caught my attention. When discussing the number of SMT thread in Zen the topic turned to Skylake and Kanter made a comment about Intel never saying anything about Skylake only supporting two SMT threads

Given the recent discussion about Power8 (drown from the Haswell-EX article): http://forums.anandtech.com/showthread.php?t=2430709. I wonder if Intel, in an attempt to surpass IBM's Power systems, is seriously looking at a 4 way SMT core? It is a logical next step.

Any thoughts?

 

[Arachnotronic]

Given that Intel is doing separate Skylake/Skylake Server cores, I'd say anything is possible.

 

[Ajay]

Given that Intel is doing separate Skylake/Skylake Server cores, I'd say anything is possible.

We that is a key enabler - the new level differentiation that Intel is doing with server cores. I just also found it interesting that Kanter said that - thinking to myself "why would he say that unless he had heard something to that effect". It's not proof, but I wonder if anyone (who can talk about it) has heard any such rumblings.

 

[Arachnotronic]

We that is a key enabler - the new level differentiation that Intel is doing with server cores. I just also found it interesting that Kanter said that - thinking to myself "why would he say that unless he had heard something to that effect". It's not proof, but I wonder if anyone (who can talk about it) has heard any such rumblings.

Here's the thing: Intel's data center group is now so ridiculously profitable on its own that Intel could now, if it chooses to, develop a lot of custom IP for data center group use only. In fact, they're already doing so.

For example, the Knight Landing CPU -- it's a "modified Silvermont," but the modifications are so ridiculously extensive that it's more or less a new line of processor cores. Keep in mind, too, that Xeon Phi's addressable market is far smaller than the addressable market for standard Xeon processors.

tl;dr -- If Intel thinks that it could strengthen its position in servers with "modified" Core processors for Xeon chips, then it can more than justify the investment given how much cash its data center group rakes in and how paranoid Intel's management is about maintaining its share of the server market.

 

[NTMBK]

512-bit vector units, four way SMT, and a nice big fat on-package eDRAM cache to reduce latency? GIMME!

 

[Arachnotronic]

512-bit vector units, four way SMT, and a nice big fat on-package eDRAM cache to reduce latency? GIMME!

I wonder why Intel hasn't introduced eDRAM to its Xeon processors yet. Seems like a good place for it...

 

[cbn]

Any thoughts?

I was wondering about SMT-4 myself last month:

http://forums.anandtech.com/showthread.php?t=2428307&highlight=

(Basically as I understand things, adding SMT-4 means more xtors needed to be added within the core to reduce latency. However, at some point using less cores with SMT-4 is probably less expensive than using a greater number of cores with SMT-2. Where Intel strikes the balance, of course, is the question.)

P.S. As mentioned in the thread, MorphCore is another thing to consider for the future.

 

[Ajay]

I was wondering about SMT-4 myself last month:

http://forums.anandtech.com/showthread.php?t=2428307&highlight=

(Basically as I understand things, adding SMT-4 means more xtors needed to be added within the core to reduce latency. However, at some point using less cores with SMT-4 is probably less expensive than using a greater number of cores with SMT-2. Where Intel strikes the balance, of course, is the question.)

P.S. As mentioned in the thread, MorphCore is another thing to consider for the future.

Well, I just printed out the MorphCore doc. After a real quick scan, I surprised that it only increases performance by 10% (ave.) over two way SMT, but Intel cores aren't designed from the beginning to leverage SMT so fully. Given that, it doesn't make as much sense to go to SMT-4 on x86 as it did for Power.