Skylake-EP/EX 28 Cores L3-Cache 38.5 MB

[csbin]

https://www.computerbase.de/2016-09/skylake-ep-28-kerne-server-cpu-cache/

 

[Sweepr]

We know.

 

[frozentundra123456]

Do you think KL-X will have solder instead of TIM?

 

[Lepton87]

Why does it have so little L3 cache? Broadwell Xeons tops out at 60MB L3. There is a serious reduction, maybe they increased the speed of the cache, Xeons with lots of L3 cache have slower l3 cache then lower end skus.

 

[krumme]

What about less l3 as a costeffective response to 32c zen?

 

[mnewsham]

I'd take a smaller L3 if they gave me a nice 128 or 256mb L4 cache.

 

[daniel1926]

I would strongly suspect that this means that the chip will have a healthy helping of L4 edram. From a performance perspective, it makes sense to have a smaller, but faster, L3 and a larger, but slower, L4. The real question is what is the communication penalty for an off chip, but on package, eDram cache and is the overall performance of the memory subsystem substantially higher despite this penalty (in typical server workloads). For my own purposes (highly parallel, memory intensive scientific-ish computing), it seems like a trade off that I would be more than happy making. And, as someone who has only recently branched out into this area from theory, it would certainly make it easier to cache optimize my data structures.

 

[Edrick]

I would strongly suspect that this means that the chip will have a healthy helping of L4 edram. From a performance perspective, it makes sense to have a smaller, but faster, L3 and a larger, but slower, L4. The real question is what is the communication penalty for an off chip, but on package, eDram cache and is the overall performance of the memory subsystem substantially higher despite this penalty (in typical server workloads). For my own purposes (highly parallel, memory intensive scientific-ish computing), it seems like a trade off that I would be more than happy making. And, as someone who has only recently branched out into this area from theory, it would certainly make it easier to cache optimize my data structures.

IBM Z series (mainframe) and Power series system already utilize this process. I would not be surprised to see Intel follow suit.

I also suspect that Skylake Xeon will have 512kb L2 which is needed for AVX512.

 

[2blzd]

so 1151 Kaby's get TB3.0 and the higher-end Kaby-X's do not?

makes sense.