Skylake chipset free pcie lanes - how many?

[bononos]

This THW article says that free pcie lanes on skylake chipsets depends on how many devices are hanging off sata/usb connectors and not the max pcie support in the spec (Z170 - 20, H170 - 16).

I assume the cpu provided pcie lanes (PCI Express Configurations ‡ Up to 1x16, 2x8, 1x8+2x4) are only used when there is a gpu plugged in.

Does that mean that a Z170 mb has 20 free lanes and could in theory support x8, x8, x4 assuming that there are 3 free pcie sockets (x8 x8 x4 length) for non-gpu expansion cards (if no sata/usb ports are used)?
And that if every sata/usb/Gbe socket was filled/used, then the free pcie lanes would be limited to 9 to be shared out among the pcie sockets (say x4 x4 x1).

Edit-
I understand now what HSIO is in relation to available pcie-lanes.

 

[LTC8K6]

I think this varies by board and mfg?

http://www.gigabyte.us/products/product-page.aspx?pid=5495#sp

 

[Pandasaurus]

This THW article says that free pcie lanes on skylake chipsets depends on how many devices are hanging off sata/usb connectors and not the max pcie support in the spec (Z170 - 20, H170 - 16).

That's not quite what it says. The SATA/USB/etc all use those PCIe lanes. You get the same number of lanes regardless of how many ports you have/use. From my understanding, you get 6 USB3.0 ports in addition to the PCIe lanes provided by the chipset. So, if you have 20 lanes, and use 6 USB3.0 devices, you'll still have 20 lanes available. A single 1GbE port makes that 19 lanes. Add say... 4x SATA drives, you've got 15 lanes left. Add an M.2 NVMe SSD (PCIe x4), 11 lanes left. My understanding is the lanes are available as long as the port isn't in use. So if your board has 8 SATA ports but you're only using 2, the other 6 lanes should still be available.

Unless I'm wrong.

I assume the cpu provided pcie lanes (PCI Express Configurations ‡ Up to 1x16, 2x8, 1x8+2x4) are only used when there is a gpu plugged in.

Not sure exactly how that functions.

Does that mean that a Z170 mb has 20 free lanes and could in theory support x8, x8, x4 assuming that there are 3 free pcie sockets (x8 x8 x4 length) for non-gpu expansion cards (if no sata/usb ports are used)?
And that if every sata/usb/Gbe socket was filled/used, then the free pcie lanes would be limited to 9 to be shared out among the pcie sockets (say x4 x4 x1).

See above. But, basically... Yes. I think. Maybe.

Or I might be completely wrong with everything here, in which case I'm sure someone will correct me shortly.

 

[wingman04]

Skylake has 20 lanes, 16 for Graphics, 4 for DMI 3.0

 

[bononos]

That's not quite what it says. The SATA/USB/etc all use those PCIe lanes. You get the same number of lanes regardless of how many ports you have/use.......

Thats not what the article says. HSIO is something new for Skylake.
"It turns out that the connectivity specs Intel reported on its 100 series chipsets are just the max supported connections". Max not available. "Similarly, none of the SATA ports are configured by default and can be configured onto various HSIO lanes, but this too will reduce the number of PCI-E lanes available"

Skylake has 20 lanes, 16 for Graphics, 4 for DMI 3.0
......

No the 16x pcie lanes on the cpu is only for plugged in GPUs. The DMI doesn't supply any pcie lanes, its just the bandwidth of the connection btwn the CPU and the northbridge(to use the old term).

 

[wingman04]

DMI 3.0 has 4 lanes.

DMI 3.0, released in August 2015, allows the 8 GT/s transfer rate per lane, for a total of four lanes and 3.93 GB/s for the CPU–PCH link. It is used by two-chip variants of the Intel Skylake microprocessors, which are used in conjunction with Intel 100 Series chipsets;[3][4] some variants of Skylake will have the PCH integrated into the die, effectively following the system on a chip (SoC) design layout.[5] On 9 March 2015, Intel announced the Broadwell-based Xeon D as its first platform to fully incorporate the PCH in an SoC configuration.[6] https://en.wikipedia.org/wiki/Direct_Media_Interface

 

[bononos]

DMI 3.0 has 4 lanes.

I suggest you actually read the article. Hint- Try and look for the "graphics" and "DMI" lanes you are referring to in the diagram.

 

[wingman04]

DMI 3.0 has 4 lanes.

I suggest you actually read the article. Hint- Try and look for the "graphics" and "DMI" lanes you are referring to in the diagram.

That Diagram you posted is the Intel chipset lanes also peripherals not the skylake lanes.
Each Intel chipset has a different setup of peripherals and lanes also DMI 3.0 and 2.0 Speed.
The chipset is the Intel 100 Series chipsets like H110 to Z170 is a chipset also called south bridge also named PCH (Platform Controller Hub). To identify the Chip, it is on the motherboard south of the CPU, that they use a heat sink on it.

DMI is (Direct Media Interface) it takes all the data from from the Chipset and transports the data to the skylake CPU via four lanes.
You should have a read with the wikipedia links and Quote I provided below.

DMI 3.0, released in August 2015, allows the 8 GT/s transfer rate per lane, for a total of four lanes and 3.93 GB/s for the CPU–PCH link. It is used by two-chip variants of the Intel Skylake microprocessors, which are used in conjunction with Intel 100 Series chipsets;[3][4] some variants of Skylake will have the PCH integrated into the die, effectively following the system on a chip (SoC) design layout.[5] On 9 March 2015, Intel announced the Broadwell-based Xeon D as its first platform to fully incorporate the PCH in an SoC configuration.[6]

DMI 2.0, introduced in 2011, doubles the data transfer rate to 2 GB/s with a ×4 link. It is used to link an Intel CPU with the Intel Platform Controller Hub (PCH), which supersedes the historic implementation of a separate northbridge and southbridge.[2]:14

https://en.wikipedia.org/wiki/Direct_Media_Interface
https://en.wikipedia.org/wiki/List_of_Intel_chipsets#100_Series_chipsets

If you look at the i7 6700k diagram below from Intel, the Graphics Has 16x lanes and DMI 3.0 has 4 lanes like I explained above here.
The Z 170 chipset has 20 PCI-E lanes and the H110 chipset has 6 PCI-E lanes.

 

[mv2devnull]

Indeed. The chipset acts as a "router" that determines which HSIO lanes can talk to the CPU at any given time. The DMI has only four lanes, so at most four lanes reach the CPU simultaneously. Intel states that traffic congestion is unlikely.

Therefore, if the lanes lead to PCIe device, the device can have at most x4 connection.

The motherboard makers are (semi)free to choose what they use the HSIO lines for. Some add further switches on the board so that you can plug, for example,either M.2 or SATA devices to same lane. (In other words, a board can have more connectors than HSIO lines, but some are mutually exclusive.)


The 16 PCIe lanes directly from CPU are not limited to graphics cards; I just built a PC with a SSD on them.

 

[bononos]

.......

If you look at the i7 6700k diagram below from Intel, the Graphics Has 16x lanes and DMI 3.0 has 4 lanes like I explained above here.
The Z 170 chipset has 20 PCI-E lanes and the H110 chipset has 6 PCI-E lanes.

Thats not right. A z170 Skylake pc has 20 pcie lanes + 16 pcie lanes from the cpu (only for gpu) which makes a total of 36 lanes. H110 has 6 pcie lanes + 16 pcie lanes from the cpu (only for gpu) for a total of 22 pcie lanes.

So the 16 pcie lanes from the cpu is not included in the 20 pcie lanes of the z170 chipset like you said earlier. The Intel pic you posted is abit misleading because it doesn't take into account of HSIO limitations which was discussed in the article I posted.

 

[mv2devnull]

The Intel pic you posted is abit misleading because it doesn't take into account of HSIO limitations which was discussed in the article I posted.

It does take those into account by using the "Up to" with the PCIe and USB. The marketing scheme is a bit misleading despite being honest.