Awww... poor you.
At the start of my third year I took a class where I had to build a complete CPU. Some specs...
It was fully piplined with the basic five stages. It was a 32-bit machine. It had level-1 instruction and data caches, both of which were two-way assosciative. It also had a combined 512KB level-2 cache that was also two-way assosciative. All caches used LRU replacement policies. It had a wallace-tree 5-cycle multiplier, and a 32 cycle divider. It had a 256 bit interface to memory. It had two parallel execution pipes. It had a 1024 entry branch predictor and a branch lookup table.
It would have had four pipelines and out-of-order execution with a 64-instruction window and the ability to speculate across four branches at once, if only there had been more time.
Pull yourself together, this isn't that hard.