This is what I gather from the site linked to below.
You have 4 values there...
tRCD (RAS to CAS delay) - the delay in clock cycles from the time the row is activated until the CAS command can be given
CAS Latency (Column Address Strobe) - the delay from the time the CAS signal is sent to the time data is available
tRP (RAS precharge) - the delay in clock cycles needed to deactivate the active row before it can access another row
tRAS - the minum amount of time in clock cycles from the time the row becomes active (tRCD) to the time the row is deactivated (tRP)
So a speed of 3-4-4-8 means it takes 3 clock cycles for the row to be activated, then it takes 4 clock cycles for the read command to be issued till data is available, then it takes 4 clock cycles for the row to be deactivated... and the last spec just says it must take no shorter than 8 clock cycles for the previous 3 events to happen, which as you can see, shouldn't make a difference since at minimum it takes 11 clock cycles for those 3 events to happen.
There's also a 5th spec that you didn't mention
Command Rate - the delay in clock cycles from the time the chip (the individual chip on the memory "stick") is selected until commands to activate row, etc. can be made
Corsair's Explanation
*EDIT*
This sheds some light into Duvie's "timing vs clock speed" thread. These measurements of clock cycles are in reference to the speed of the RAM... so... think about it.
Lets say you're running 3-4-4-8, it takes a minimum of 11 clock cycles for the RAM to be accessed. Lets also say you're running a P4 2.4C @ 3.0 Ghz on a 250 Mhz FSB with 1:1 memory ratio. At 250 Mhz, that's 250 million clock cycles per second, and this operation takes a minimum of 11, so if you divide 250 million by 11, you get about 22.7 million, which is the maximum times RAM can be accessed in one second with a 250 Mhz FSB with 3-4-4-8 RAM timings.
So lets say you run a RAM divider and get the RAM speed back down to 200 Mhz, and that allows you to run 2-2-2-6. That means it takes a minimum of 6 clock cycles for RAM to be access. So lets figure it out again. 200 million divided by 6 = about 33.3 million times the RAM can be accessed in one second with a 200 Mhz FSB with 2-2-2-6 RAM timings.
This doesn't take one thing into consideration. The amount of data being read. Once a CAS command is given to read the data, it can read as much data from that row as it needs until it needs to move to a different row to read. That's where the clock speed makes a difference, once the CAS command is given, you have more memory bandwidth at 250 Mhz than at 200 Mhz, so the whole row of data can be read faster at 250 Mhz than at 200... BUT it will need more time to move to the next row.
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