Actual uOps in CPU are rather large, and optimized towards execution intricacies of exact micro architecture. I vaguely remember uOP size of ~90bits already during some old generation of 32bit code and register starvation. Who knows how large they are now?So I guess what I'm asking is can the x86 instructions be converted into micro-ops by the compiler and would it help the CPU to have a front end that deals only with micro-ops?
x86 Instructions are converted into MicroOps since the P6 Pentium Pro, not P5 Pentium.I'm not an expert so go easy on me but since x86 are "converted" into micro-ops in CPU's since the Pentium would it be possible to somehow compile software directly into micro-ops?
I have read that decoding complex instructions into micro-ops is a power hungry and cycle hungry business.
If it were possible to compile straight to micro-ops then the entire decode to micro-ops part of the front end could be skipped all-together it seems?
So I guess what I'm asking is can the x86 instructions be converted into micro-ops by the compiler and would it help the CPU to have a front end that deals only with micro-ops?
Yes I forgot the Pentium was the first superscaler, not microo-ops.x86 Instructions are converted into MicroOps since the P6 Pentium Pro, not P5 Pentium.
You would need a Processor that supports bypassing the x86 decoder frontend to feed it MicroOps directly. And also, the MicroOps would be pretty much a new ISA itself, and bound to THAT specific Processor generation. You have no way to do this since unless it is a currently available hidden secret functionality (Which I would not be surprised, yet don't expect to be found, either), you can't send MicroOps to the Processor directly. It is entirely internal.
Somewhat related... Check THIS.With big.LITTLE designs, and the uuuge amount of cores we are getting, couldnt they just sport a few "old" x64 cores to run legacy apps on and the rest be new and fast cores? Like a slowold.NEWFAST design sort of thing? .
Basically, first Itanium had a x86 decoder in it that translated x86-to-IA64, which was obviously bypassed in IA64 mode (I recall reading that early Itaniums had a x86 core on them, but seems to be that translator decoder. I don't recall if early Itaniums were demoed running standard x86 Windows XP or something like that, but is theorically possible). Also, the 460GX Chipset for Itanium had a whole bunch of PC/AT baggage on it, like a PIC (Programmable Interrupt Controller) with a 8259A compatibility mode. Basically, Intel created a new architecture and platform from the ground up then tainted it with the legacy of the previous architecture and platform.Actually, when we created Merced (1st Itanic) it was designed to be able to be FULLY backwards compatible (i.e. boot MS-Dos 1.0). 25%-33% of the chip was actually a HARDWARE ia32 to ia64 translation engine.
You could put the chip is EPIC (ia64) mode and everything would run though the normal pipeline or ia32 mode and things 1st ran through the ia32 translator then most of the normal pipline. Yeah, you took a performance hit in ia32 mode, but it was the price you paid for "100%" backwards compatibility.
So, I am not sure why the change to a software emulator, unless:
1) they ditched the hardware emulator to get back some real estate of the die, or
2) they didn't like the switching the chip between ia32 & ia64 bit modes.
The rumor is that they did not remove it. Once you disable small cores, AVX512 is back. Outright horrible choice that will kill AVX512 on where it would matter the most.Didn't Intel removed the AVX-512 unit of the big Core on a big.LITTLE Processor (Alder Lake it was?) since all them had to support the same instruction sets?
Nothing of "such new instructions could be used to support the decoder handling variable length CISC code faster" you quoted suggests an "ISA, which is a totally different instruction set that's fixed length".Well sure, Intel could introduce a new CPU that executes the "x86+" ISA, which is a totally different instruction set that's fixed length
You must have a lot of experience and knowledge (I'm sure it was researched as well) in the industry to be able to write such a detailed and exhaustive historical account of the x86 architecture.Been writing and rewriting it on/off for like, 4 or 5 years. I hope someone else enjoys it. Note that I'm hotlinking a lot of heavy PDFs so you may not want to click too much, so I may have to cleanup it...
Don't forget that we're not only carrying legacy x86 stuff from 40 years ago, but also remants from the IBM PC platform. We're tainted with support chips from the Intel 8080/8085 CPU from BEFORE the 8086/8088.
It was actually intending to build a case that we have to burn the PC-x86 platform with a flamethrower and start from scratch again, heh.You must have a lot of experience and knowledge (I'm sure it was researched as well) in the industry to be able to write such a detailed and exhaustive historical account of the x86 architecture.
Does the microcode have any hidden features, opcodes or easter eggs that have not yet been documented?
It does! Using the REP or REPNE prefix with a MUL or IMUL instruction negates the product. Using the REP or REPNE prefix with an IDIV instruction negates the quotient. As far as I know, nobody has discovered these before (or at least documented them).
Amazing! Thanks for sharing. The grand daddy of them all!
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