Isn't the 3900x 4 CCX's with 3 cores in each one, basically, 3+3+3+3 cores.
I'm curious about this too, but I don't currently believe that to be the case.
In Zen and Zen+ archtecture (basically same arch. arrangement, just a small shrink that enabled higher clocks / greater power efficiency between then), they had CCXs, which (simplistically) was a grouping of four CPU cores, and a slice of L3 cache. Each Zen/Zen+ die had two of those CCXs.
Newer Zen2 architecture, has them arranged in a CCD, which houses two CCXs, and talks to an "I/O die" to connect to memory. There can be multiple dies with CCDs connected to the I/O die. Anyways, however it works, it supposedly did away with the "NUMA penalty", which means that for all practical purposes, AMD no longer has to "balance" CCXs to equal core counts.
So, I believe, it's possible to bin a CPU die with one CCD, containing two CCXs, with one CCX containing only two good cores, and the other CCX containing all four good cores, as a six-core CPU die, and pair up one or two of those dies with an I/O die, for a Zen2-architecture Ryzen 3000-series CPU.
Certainly, if this is true, and I haven't seen much about it, or anything against this idea, then it would make defect-related binning a lot easier.
I could be completely off-base here, though, and possibly, if they have a CCD, with one CCX with four good cores, and one CCX with one bad core, then they HAVE TO disable one CCX in the four-core CCX, to make 3+3 cores in each CCX, to sell as a 6-core CPU die. I think that would be an unfortunate outcome, though.
*** Anandtech main page editors, maybe a deep dive on this issue would make a good article, what with ThreadRipper 3 coming up now too. (Maybe it's covered in that article? Will have to read it.)