Should Clawhammer use an FPU at 1.33X to compensate for its lower clock speeds?

[MadRat]

With the Opteron and Athlon 64 slated at lower clock speeds that the current Athlon Thoroughbred, it seems to me to make sense to use a higher multiplier on the FPU unit to compensate for the lower clock speeds. I don't want a 'Hammer chip if its going to drop off performance in the areas where the Athlon XP was strong. I'm guessing that people that read the x-bitlab's preview are all thinking the same thing, the 'Hammer needs some fine tuning to make its performance relative to the Athlon XP...

So in your opinion should Clawhammer, the consumer 'Hammer, at least use an FPU at 1.33X to compensate for its lower clock speeds? Don't forget to vote.

 

[Idontcare]

Originally posted by: MadRat
With the Opteron and Athlon 64 slated at lower clock speeds that the current Athlon Thoroughbred, it seems to me to make sense to use a higher multiplier on the FPU unit to compensate for the lower clock speeds. I don't want a 'Hammer chip if its going to drop off performance in the areas where the Athlon XP was strong. I'm guessing that people that read the x-bitlab's preview are all thinking the same thing, the 'Hammer needs some fine tuning to make its performance relative to the Athlon XP...

So in your opinion should Clawhammer, the consumer 'Hammer, at least use an FPU at 1.33X to compensate for its lower clock speeds? Don't forget to vote.

I'm not sure what you are writing makes any sense. You imply you are writing about running 2 seperate clocks on a cpu and asynch'ing the FPU from the core?

 

[Rectalfier]

Maybe they could add another floating point unit in there.

 

[zephyrprime]

What you're proposing makes no sense. If they could do that, they'd just make the entire chip faster. The P4 has double pumped ALUs but all ALU ops also take twice as long to do.

 

[dexvx]

If such a procedure was remotely possible, it'd take another product cycle to implement, just like adding a FPU unit.

 

[MadRat]

How could they add a fourth FPU unit? I thought the three FPU unit architect was effectively maxed out.

 

[andreasl]

I think you should leave chip design to chip designers 🙂 Do you honestly believe they would be able to make that kind of change within the small timeframe and still release it in September??

 

[MadRat]

Originally posted by: andreasl
I think you should leave chip design to chip designers 🙂

Engineers need prodding our we'd still be trapped in the world of pre-incandescent lights.

 

[JeremiahTheGreat]

I wonder how feasible having a CO-processor is for the A64 achitecture, say to enable SSE, SSE2 and hyperthreading. It would be much much less complex than the normal CPU (which would be stripped of these), which means it can run at a higher speed. And it would cut costs, as happy little dell buyers with their intergrated video cards have no need for these instructions, but meanwhile the hardcore gamer does (and is willing to pay). I know i know.. it'll never happen.

 

[andreasl]

Originally posted by: MadRat

Originally posted by: andreasl
I think you should leave chip design to chip designers 🙂

Engineers need prodding our we'd still be trapped in the world of pre-incandescent lights.

My guess is that any engineer reading this thread would be laughting..

 

[zephyrprime]

Engineers need prodding our we'd still be trapped in the world of pre-incandescent lights.

What are you talking about?! Edison was a hard core inventor! He needed so much "prodding" that he had his first patent before he left his teens. He introduced light bulbs to a world that thought you couldn't do any better than the gas lamp!

I wonder how feasible having a CO-processor is for the A64 achitecture, say to enable SSE, SSE2 and hyperthreading. It would be much much less complex than the normal CPU (which would be stripped of these), which means it can run at a higher speed. And it would cut costs, as happy little dell buyers with their intergrated video cards have no need for these instructions, but meanwhile the hardcore gamer does (and is willing to pay). I know i know.. it'll never happen.

Stripping out stuff always makes chips cheaper but probably not as much as you'd think. We're really paying for R&D and fab equipment more than marginal production costs when we buy CPUs and stripping out parts would not reduce either of these costs. Plus, doing so would slow SSE way, way down. (too young to remember FPU coprocessor performance on 386s?) Also, it'd be impossible to delegate hyperthreading.