Should AMD include a small iGPU die variant for their upcoming 4C/8T Zen APU?

[cbn]

I was talking hypothetically, why dedicate a large die size area for a worthless 128 Shader iGPU ??? APUs are all about iGPU performance, smallest Kaveri APU already has 256 Shaders (A6-7400K) at 28nm, why spend money/resources for a 14nm 128 Shader iGPU ?? Not worth it.

Right now I have three Jaguar SOCs (E1-2100, Sempron 2650, Athlon 5350) and IMO they all have too much iGPU relative to the CPU.

For example, my Athlon 5350 in Team Fortress 2 @ 1080p low will get avg. FPS somewhere over 30 FPS, but it will still chug in the low 20's. Lowering resolution doesn't help that problem whatsoever due to CPU bottleneck.

So instead of four Jaguar cores and 128sp iGPU, I would like to see something with more CPU grunt. Replacing four Jaguar cores with four Zen cores would be ideal IMO. And for non-gamers (and gamers that use dGPU) having extra CPU will be of greater benefit than adding more iGPU.

P.S. Here were my test notes on Athlon 5350 and Team Fortress 2 from last year:

http://forums.anandtech.com/showpost.php?p=36794469&postcount=287

I'm done with the first phase of multiplayer testing for Athlon 5350 on Team Fortress 2.

(This phase involved changing resolution with the lowest detail settings being used as a constant.)

Some basic observations:

1. The game appears to spread the load out primarily to three cpu cores. (Activity does exist on core four, but it is extremely light)

2. Some player character classes appear to stress the game more than others. For example, I seem to get the lowest frame rates while playing the Scout.

3. According to FRAPS minimum frame rates have dropped to as low as 16 on multiple logs. I have tested this on resolutions as low as 800 x 600 with lowest settings and it still happens.

4. Determining average frame rate is extremely difficult because once my player dies (and I am waiting to respawn) the frame rate shoots up much higher than what it was in game. With that mentioned, average frame rate appears to be > 30 FPS up to 1920 x 1080 (lowest settings). Some variation in average FPS appears to be dependent on map and number of players.

Overall, I will give the Athlon 5350 a pass (for casual gamers) on Team Fortress 2 up to 1920 x 1080 (lowest settings). However, the minimum frame rates reported by FRAPs can be alarmingly low. As I have mentioned, lowering resolution does not help the reported minimums. Ideally I would like to see AM1 with a higher clock on the CPU in order to help the minimum FPS.

 

[os2wiz]

Should AMD include a small iGPU die variant for their upcoming 4C/8T Zen APU?

Of course they should, as you can not have HSA capability without the compute cores of an igpu. AMD to be true to its mission for HSA adoption should have a small apu at least , even its most powerful cpus. Others are speaking from ignorance when they say no.

 

[os2wiz]

I was talking hypothetically, why dedicate a large die size area for a worthless 128 Shader iGPU ??? APUs are all about iGPU performance, smallest Kaveri APU already has 256 Shaders (A6-7400K) at 28nm, why spend money/resources for a 14nm 128 Shader iGPU ?? Not worth it.

You are so far off the mark it is not funny. Do you understand patrallel computing. Do you know anything about HSA architecture? An igpu with compute cores with powerful cpu cores is the future of computing applications can execute 3-4 times faster with a decent iGPU on the die with strong cpu cores when optimized for HSA. Optimization is not a big deal and can be accomplished with minimal resources by ISV's, HSA will hopefully be on track within the next 2 years as more software vendors see the huge performance increases their applications can achieve. Zen without an igpu is castrated.

 

[AtenRa]

You are so far off the mark it is not funny. Do you understand patrallel computing. Do you know anything about HSA architecture? An igpu with compute cores with powerful cpu cores is the future of computing applications can execute 3-4 times faster with a decent iGPU on the die with strong cpu cores when optimized for HSA. Optimization is not a big deal and can be accomplished with minimal resources by ISV's, HSA will hopefully be on track within the next 2 years as more software vendors see the huge performance increases their applications can achieve. Zen without an igpu is castrated.

You are new here and dont know me, but you can check my latest reviews here and here to get a picture.

Im not saying not to include an iGPU in the mobile APUs, im saying a small 128 Shader iGPU is not viable for a 14nm FF Quad Core ZEN APU.

 

[cbn]

Im not saying not to include an iGPU in the mobile APUs, im saying a small 128 Shader iGPU is not viable for a 14nm FF Quad Core ZEN APU.

Why does the iGPU need to be bigger?

Remember not everyone will be using Power User OpenCL apps or gaming.

 

[bononos]

Even if you are talking about mainstream APUs, i would also say no. Either you buy an APU for its strong iGPU performance or you by a CPU.

So if you want a CPU, I would prefer the die area occupied by any iGPU to be used for more cash/extra core or to make the CPU smaller = cheaper.
Why add a small iGPU when in the same area you can put another Core and sell a 6C 12 T CPU for the same price as a 4C 8T + small iGPU ??
......

Its made alot of sense for Intel to stick an igpu on its cpus since users who are not into gaming don't have to shell out for a separate card. And Intel is a better bang/buck for people who don't need a dgpu.

Maybe AMD can't stick in an igpu for their FX cpus is because they can't get the die size down to where it is viable.

 

[Enigmoid]

You are new here and dont know me, but you can check my latest reviews here and here to get a picture.

Im not saying not to include an iGPU in the mobile APUs, im saying a small 128 Shader iGPU is not viable for a 14nm FF Quad Core ZEN APU.

I agree. On 14nm 128 shaders is so ridiculously tiny (~5 mm^2) that it makes no reason not to go for 256 shaders. The display controller and media capabilities will be vastly larger than the 2 CU shader array. Adding another 128 shaders only adds a tiny amount to the die size but potentially doubles graphics power.

 

[ShintaiDK]

Yep, 256/384 would be minimum on 14nm. You still need UVD block and what else to support the IGP nomatter shader amount.

 

[cbn]

The display controller and media capabilities will be vastly larger than the 2 CU shader array.

Why do you think the display and media would be vastly larger than the 2 CU array?

 

[cbn]

Yep, 256/384 would be minimum on 14nm. You still need UVD block and what else to support the IGP nomatter shader amount.

For a mainstream chip that will probably using a single stick of 8GB DDR4 3200, I think 384sp would be too much when combined with 4C/8T.

Now granted, I think the chip should have a dual channel memory controller (for use with two slower 4GB sticks), but my expectation (2+ years into the future) is that a single 8GB stick will be the sweet spot on cost for RAM.

 

[Dresdenboy]

Yep, 256/384 would be minimum on 14nm. You still need UVD block and what else to support the IGP nomatter shader amount.

The non shader stuff will shrink, too.

BTW with accepted TDPs coming down, there is even a need to have some significant parallel processing capabilities as more and more applications use them. Using the SMT cores doesn't count for these tasks as they still waste a lot of power for doing simple parallelizable stuff. GPU cores can still get the most performance out of the given TDP. FPGA gates even more so (if they don't have to switch the logic too frequently).

 

[velis]

A note to consider: thread title says "a small iGPU". It doesn't specify what small means. By the time ZEN comes out, AMD may consider 512 shaders as "small" or even "very small". It's moot to bicker about 128 vs 256 when we all don't know AMD's plans.

The question however remains valid: is it sensible to include an iGPU in all SKUs or not?

The question doesn't ask about full-power APUs that are meant to be standalone, it also doesn't ask about full version of Fury being attached to CPU together with 4GB HBM cache. It asks merely if ZEN SKUs should or should not include any sort of GPU. Doesn't even distinguish among top bin and mainstream SKUs.

Edit: though a top bin ZEN + Fury + 4GB HBM cache would really be something!

 

[Blitzvogel]

The question however remains valid: is it sensible to include an iGPU in all SKUs or not?

Yes, especially when the design might be used in the mobile space too. A smallish (256 SP) iGPU in high end desktop and server systems will be appreciated if someone encounters an issue with their dGPU, but at the right clocks (>1 GHz) could still be powerful enough for OpenCL and HSA in combination with the x86 cores.

Big iGPUs are best saved for the mobile and consumer desktop space where package integration, cost, and value is more paramount in driving consumer experiences across a broad type of applications. A quad core Zen with 768 SPs or maybe even 1024 SPs is a reasonable APU with enough possible binnings to cover the bases, including the possibility of an HBM equipped model at the top end.

 

[cbn]

A note to consider: thread title says "a small iGPU". It doesn't specify what small means.

Think of "small iGPU" as a processor sized to basic tasks (Video, accelerating the UI,etc) with gaming/power user open CL apps as a target of lesser importance.

IMO, such an iGPU for 4C/8T should be based around the bandwidth of one 8GB stick of DDR4 3200 (though with that mentioned the chip should have a dual channel controller for versatility) . With a cut down/die harvested 2C/4T SKU most likely being used with a single 4GB stick of DDR4 2133 or DDR4 2400 economy RAM.

So the question how big should that iGPU be?

Single channel DDR4 3200 is 25.6 GB/s bandwidth, but remember the latency is higher than dual channel DDR3 1600 (which is also 25.6 GB/s).

Single channel DDR4 2400 is 19.2 GB/s, but remember the latency will be higher than the same amount of bandwidth in DDR3.

 

[cytg111]

..
So the question how big should that iGPU be?

Single channel DDR4 3200 is 25.6 GB/s bandwidth, but remember the latency is higher than dual channel DDR3 1600 (which is also 25.6 GB/s).

Single channel DDR4 2400 is 19.2 GB/s, but remember the latency will be higher than the same amount of bandwidth in DDR3.

They should ship Zen with soldered-on HBM for main memory, 8/16/32G variants. How many really upgrades the main memory banks mid-cycle?

 

[Enigmoid]

They should ship Zen with soldered-on HBM for main memory, 8/16/32G variants. How many really upgrades the main memory banks mid-cycle?

Not many. But I would to reuse memory for a new build.

HBM would massively reduce PCB space and power usage so it would be a net win.

 

[cbn]

They should ship Zen with soldered-on HBM for main memory, 8/16/32G variants. How many really upgrades the main memory banks mid-cycle?

It adds cost (TSV in DRAM dies, interposer, logic chip, etc.).

Also the HBM implementation described in the Anandtech article here was quoted at 14.6W for 4GB at 512 GB/s. How soon can AMD get that power consumption down and a what cost compared to commodity DDR4?

 

[ShintaiDK]

They should ship Zen with soldered-on HBM for main memory, 8/16/32G variants. How many really upgrades the main memory banks mid-cycle?

It may be too early by 1-2 years due to cost. But else absolutely agree. Its something that have to happen.

If we look at Intels 2017 Purley platforform Skylake-EP/EX. It looks like HMC+PCM there. Fixed stacked DRAM for main memory is coming before 2020 for endusers. I think we could see it as the norm already in 2018. Maybe on AMDs Zen APUs in 2017. But for 2016 its not going to happen.

 

[cbn]

It may be too early by 1-2 years due to cost. But else absolutely agree. Its something that have to happen.

If we look at Intels 2017 Purley platforform Skylake-EP/EX. It looks like HMC+PCM there. Fixed stacked DRAM for main memory is coming before 2020 for endusers. I think we could see it as the norm already in 2018. Maybe on AMDs Zen APUs in 2017. But for 2016 its not going to happen.

For a Zen consumer APU in 2017, the SoC power consumption will limit how large that iGPU can be (regardless of bandwidth).

So whatever AMD develops to solve that problem on the comsumer device level is going to have to be cost effective enough to work within that limitation.

And as far as iGPU size goes, I think most people are going to find diminishing returns in that rather quickly. For mainstream I see smaller iGPUs and good battery life being more important.

 

[Blitzvogel]

HBM sounds all well and good for APUs, but for the sake of meeting so many needs, an HBM supporting APU still needs to support regular DDR3/4 system memory. The cost and heat of going HBM only would likely be too much.

For instance, a 4-core Zen with 1024 SPs would be perfectly at home with a single 2 GB HBM module or two 1 GB HBMs (better bandwidth) specifically operating as VRAM and/or an L3/L4 cache. You would still have external DDR3/4 system RAM but it would save the headaches of HBM cost and having too much heat in a centralized source.

4 Zen Cores, 1024 SPs at 1 GHz with 2 x 1 GB HBM modules for 200+ GB/s and 8 GB of DDR4 sounds like a pretty sweet and relatively cheap mobile gaming setup.

The ability to equip with 1-4 HBM modules of varying sizes along with system RAM sounds like a very nice way to customize products for specific niches. You just have to hope that there is actual availability in real world products, which has been such a huge problem for AMD.

Going HBM-only on an APU would be expensive (8+ GB), but there could be a niche for it for small PCs, as it eliminates the board space and traces for regular system RAM. I'm not sure if scientific computing needs massive amounts of memory like CGI rendering does.

 

[cbn]

For specs on a quad core Zen APU "Mini" here is what I would want to see:

TDP: 15W (2C/4T) to 65W
CPU cores: Zen in 4C/8T, 4C/4T, 2C/4T configurations
L2 cache: 1 MB per core (later versions could have 2MB per core)
L3 cache; None
Memory controller: dual channel DDR4 (However, I think most OEMs will probably use with one 8GB DDR4 3200 stick at the high end and one 4GB DDR4 2400 stick at the low end)
iGPU: 128sp (later versions might have 256sp)
8 to 16 PCIe lanes
two SATA 6 Gbps (integrated, so chip is a SoC)

Basically a replacement for cat core SoCs, but instead of adding more iGPU to the die (via increased xtor budget from die shrink) the CPU part gets beefed up instead (quad Cat core --> quad Zen Core)

 

[cbn]

A nice bonus would be if AMD designed the Zen APU with chop lines, this way both large iGPU and small iGPU Zen APUs could be derived from one original layout.

P.S. Here is an article from Real World tech with some discussion on chop lines ----> http://www.realworldtech.com/sandy-bridge-circuits/

(See below is Sandy Bridge and its chop options)

 

[Dresdenboy]

Those chop lines help to create the final layout more easily. They don't make it possible to cut the final silicon accordingly. AMD might do this and also the mentioned ring bus. The XBar of Orochi likely is faster, but uses more power and would scale in complexity.