The P4 architecture is VERY dependant on memory bandwidth, and the Celeron (castrated P4 Willamette) even more so.
SDRAM is castrating it even more, not providing nearly as much memory bandwidth as is needed. DDR provides much more memory bandwidth, which is what the P4 architecture requires.
Also, Seti@home loves high memory bandwidth and memory speeds, due to all the data and the calculations it does 🙂
Confused