ServeTheHome：AMD EPYC Rome Details Trickle Out 64 Cores 128 Threads Per Socket

[csbin]

https://www.servethehome.com/amd-epyc-rome-details-trickle-out-64-cores-128-threads-per-socket/

New AMD EPYC Rome Generation Disclosures
The next generation of AMD EPYC 7000 series is shaping up to be a Xeon killer. The next-generation AMD EPYC 7000 series is codenamed “Rome” and it is going to be a big deal. Instead of adopting Zen+ like the desktop Ryzen CPUs, the new EPYC generation will use the Zen 2 architecture which means improved IPC gains from two generations of core tweaks. Beyond the IPC gains, the next generation parts will be based on 7nm production.

The impact of leapfrogging Intel and using 7nm is several-fold. First, Rome will have up to 64 cores and 128 threads in a single socket. The new CPUs will be socket compatible with the current SP3 socket motherboards with a small caveat. At STH, we expect Rome to adopt PCIe Gen 4 so motherboards will have to support the higher signaling rates to achieve PCIe Gen 4. We also expect the next generation to have greatly improved Infinity Fabric, an area that the first generation product has room to improve upon.

The other key disclosure is that AMD already has silicon in their labs with the next generation AMD EPYC Rome CPUs in their labs. They will be sampling to partners in the second half of 2018 and will launch in 2019.

This is going to put a lot of pressure on Intel Xeon as Cascade Lake is not going to come anywhere close to the core count of AMD EPYC’s next generation. Intel is scrambling to build a competitive response. 2019 is going to be extremely interesting in the server market.

 

[wahdangun]

Damm, why AMD not waiting TR2 to use this 7 NM EPYC die ?

And with pcie4 being compatible with existing motherboard, it's huge. It's mean there are no reason for socket change at all, at least until ddr5.

AMD really going for the kill, appropriate for the name.

 

[Qwertilot]

Presumably because they're expecting to sell as many of these as they can make for a decent while!

Once yields up etc etc they'll have some spare capacity to diver to thread rippers.

 

[CatMerc]

Damm, why AMD not waiting TR2 to use this 7 NM EPYC die ?

And with pcie4 being compatible with existing motherboard, it's huge. It's mean there are no reason for socket change at all, at least until ddr5.

AMD really going for the kill, appropriate for the name.

It won't be ready for Threadripper until mid next year. At that point you might as well refresh the parts now.

7nm EPYC is going through *bring up* right now, and will sample somewhere in H2 2018 to partners. That's not something that will be ready before 2019 for any real use.

 

[BigDaveX]

Remember back in the Core 2 Xeon era, when Intel stuck with an MCM set-up and got absolutely slaughtered by the same K10 cores that were struggling to stay relevant on the desktop side? Seems like whenever the whole debate about MCM versus monolithic chips comes up, Intel always chooses the wrong side at first (except for the Core 2 Quad, and even then you could argue they just got lucky due to Phenom I being a misfire).

 

[IEC]

32 core Threadripper announcement and now confirmation of 64 core Epyc CPUs next year...

My wallet is not ready.

 

[StefanR5R]

STH's headline and article make it sound as if AMD confirmed the core count of the "Rome" processor at the event. AMD didn't though, AFAICT from other press coverage. Did they?

 

[IEC]

STH's headline and article make it sound as if AMD confirmed the core count of the "Rome" processor at the event. AMD didn't though, AFAICT from other press coverage. Did they?

Now that you mention it, I tried looking for official confirmation and was unable to find any. So unless someone officially confirmed it to Computex attendees, I suppose we don't know the core count of Rome for sure quite yet.

 

[ksec]

Update from Servethehome

(Edit June 6, 2018: Mea Culpa. Looks like we got some generational information “confirmed” to us incorrectly. Expect a 48 core / 96 thread generation before a 64 core / 128 thread generation. Still quite a huge gap. DDR4 and interconnect improvement information held up to further confirmations. 64 core / 128 thread apparently is still coming, just missed one generation due to a few words not being typed in messages to us.)

 

[dacostafilipe]

So, now we are back to the 6c CCX idea?

 

[Accord99]

Remember back in the Core 2 Xeon era, when Intel stuck with an MCM set-up and got absolutely slaughtered by the same K10 cores that were struggling to stay relevant on the desktop side?

I don't. By the time Barcelona came out, it was facing 45nm Harpertown which often beat it.

https://www.anandtech.com/show/2386/12

And by the time Shanghai was out, it was only a few months away from Nehalem.

 

[moinmoin]

Update from Servethehome

"just missed one generation" lol
So Zen 2 Epyc is 48 cores and Zen 3 Epyc will be 64 cores? A tad early to rave about then.

 

[jpiniero]

So, now we are back to the 6c CCX idea?

I still think it's 4x4, but they will go with 48 cores max to start.

 

[dacostafilipe]

I still think it's 4x4, but they will go with 48 cores max to start.

I don't know. Having a 16c die and not using all the cores available is not something AMD does recently.

 

[jpiniero]

I don't know. Having a 16c die and not using all the cores available is not something AMD does recently.

They might still sell it, just not publicly. I guess it depends on how quickly AMD intends to ship this, yields might not allow for it right away.

 

[NTMBK]

So, now we are back to the 6c CCX idea?

48 and 64 are both divisible by 4 or 8. 64 is not divisible by 6. I doubt it will be 6.

 

[NTMBK]

I don't know. Having a 16c die and not using all the cores available is not something AMD does recently.

This is going to be a pretty big die (even with MCM), very early on a cutting edge process. I could see it happening.

 

[Topweasel]

This is going to be a pretty big die (even with MCM), very early on a cutting edge process. I could see it happening.

Yeah I always figured the Starship 48c on the roadmap was always a conservative yields choice. I could see them not wanting to try to push to much to get 64c to max out first gen 7nm even if yields are better than expected. So limit it to 12c on Desktop. 48c on EPYC and TR3. If yields are really good you have an option of a mid season release. But otherwise can continue to use 90+% of the dies while you work on you work on yields with Zen3.

 

[dacostafilipe]

48 and 64 are both divisible by 4 or 8. 64 is not divisible by 6. I doubt it will be 6.

STH's update talks about max 48c for 2. generation and 64c for 3. generation.

I would see a 6c CCX for "Epyc 2 on 7nm" and a move to 8c CCX for "Epyc 3 on 7nm+". That's 50% core increase per generation and that's a lot!

It would also makes sense for Ryzen 3xxx CPU and APU: Ryzen 12/32, Ryzen APU 6/12 + Vega(Navi?)

This is going to be a pretty big die (even with MCM), very early on a cutting edge process. I could see it happening.

It would be a waste to use such dies on Ryzen. 6c CCX makes more sense for me. But maybe they will make both. 6c CCX for Ryzen/Threadripper and 8c CCX for Epyc?

 

[CatMerc]

So, now we are back to the 6c CCX idea?

It's three CCX's most likely.

 

[dacostafilipe]

It's three CCX's most likely.

Yes, also a possibility.

But would this not increase latency as we have more CCXs to connect together? We would need 3 CCX connections instead of 1.

EDIT: No, it's not the case. All CCXs are connected to the IF plane and not directly to each other. Adding a new CCX would "only" require a new CCM () to be added.

 

[CatMerc]

Yes, also a possibility.

But would this not increase latency as we have more CCXs to connect together? We would need 3 CCX connections instead of 1.

EDIT: No, it's not the case. All CCXs are connected to the IF plane and not directly to each other. Adding a new CCX would "only" require a new CCM () to be added.

Yup. The IF is already built in such a way that makes it obvious they're going to add more CCX's. It's also the most power efficient route to take, those intra CCX links are hungry compared to the rest of the fabric.

 

[ksec]

Zen 3 as a platform will be expensive, as I guess it would support DDR5, which means a new Socket and New Memory Controller, may be PCI-E 5.0 as well. So the 64 Core per socket makes it a little more attractive to upgrade. But I think Zen 3 we are looking at mid to late 2020.

 

[NTMBK]

Yes, also a possibility.

But would this not increase latency as we have more CCXs to connect together? We would need 3 CCX connections instead of 1.

EDIT: No, it's not the case. All CCXs are connected to the IF plane and not directly to each other. Adding a new CCX would "only" require a new CCM () to be added.

And increasing the CCX size would increase the latency within the CCX.

 

[paperfist]

128 threads?!? My Commodore 64 is rolling around in the grave!