Serial ATA & interrupts?

[gumpish]

Hi there. I tried my darndest to read the official spec on SATA...

Can anyone tell me how the new standard will handle interrupts? As in, how many connectors will be available on a standard controller and how many IRQs will that controller need?

 

[Lord Evermore]

I presume that is up to the chipset designer. I honestly don't know why integrated IDE controllers still require two IRQs to function, when add-in controllers only require one. Maybe because the system sees the integrated ports as two separate devices to compete for attention, while the add-in controller is performing more "controller" work like a SCSI adapter and managing the data flow from the two ports and communicating it to the main chipset. Kinda wonder why no main chipset designers have ever bothered to make the integrated controller more optimized like that.

Current add-in SATA chips work just like a RAID chip for parallel IDE, or an add-in PCI controller. They use one IRQ for two extra ports. I don't know if other cards with more than 2 ports use two chips which would take 2 IRQs, or a special chip that allows 4 ports. How many IRQs it uses would depend on what design it takes. If a single chip supports 4 devices and ports, then it will only take 1 IRQ, but if they need a chip for every two ports, then it'll need more and more IRQs.

When SATA is integrated into the main chipset, I would hope they'd manage to make it only use one IRQ for all ports. However since the first SATA-capable chipsets will only have two ports (with standard IDE as well so only hard drives are expected for SATA), those two ports will probably use two IRQs. Baby steps; first they move to SATA, then hopefully redesign their controllers to use fewer IRQs.