[SemiAccurate] AMD to differentiate cores

[razvanm3]

So, new post from Charlie Demerjian on AMD Master Plan.
https://semiaccurate.com/2019/04/15/amd-to-differentiate-cores/
Is anyone willing to tell us what's the article about?

 

[Hitman928]

It's about how AMD is rumored to be differentiating CPU core design to address different markets with different compute requirements and constraints.

 

[jpiniero]

Little Zen would be nice, but not essential. I don't think there's any profit to be made for AMD, but Chromebooks are hot these days. And Dozer's just not going to cut it.

 

[razvanm3]

So they will take a more "Intel" like aproach by having different designs for consumer and enterprise products, instead of using the same chiplet for both of them.
This strategy will be used with Zen 3 or later?

 

[scannall]

I could see a 'Zen Lite' for consoles. Drop the SMT, and 8 light Zen cores would work fine for that market.

 

[NTMBK]

Haven't read the article (not a paid member), but my guess is a split similar to Intel's Skylake split- a server variant and a consumer variant. Bigger SIMD units and tweaked cache sizes for server, something closer to Zen 1 for everything else.

 

[Tuna-Fish]

Haven't read the article (not a paid member), but my guess is a split similar to Intel's Skylake split- a server variant and a consumer variant. Bigger SIMD units and tweaked cache sizes for server, something closer to Zen 1 for everything else.

I'd find the bigger SIMD units for server curious. Intel tries very hard to sell those for server customers, but I have not seen much interest outside HPC. Most normal server loads have minimal SIMD portions and run better on cores with narrower SIMD pipes.

 

[itsmydamnation]

I could see a 'Zen Lite' for consoles. Drop the SMT, and 8 light Zen cores would work fine for that market.

If this is true this is not what they are going to do, the obvious thing is really wide vectors for a HPC style CPU and then 256bit vectors for everything else. But unless the the plan is to focus GPU's far more on graphics there is going to be overlap between products.

These Zen lite idea's make no sense, if AMD wanted a low power core, they would want it to still to be just as wide as Zen, less pipeline stages, lower clocks, lower min and max voltage.

I'd find the bigger SIMD units for server curious. Intel tries very hard to sell those for server customers, but I have not seen much interest outside HPC. Most normal server loads have minimal SIMD portions and run better on cores with narrower SIMD pipes.

If AMD wants to keep pushing core counts @5nm or beyond maybe a more power focused clock limited core? Then a higher clocking core for the lower core count server/consumer. maybe even mix and match chiplets on one package


edit no 7123: or maybe a very wide (gpu wide) SIMD focused chiplet

 

[maddie]

Seeing that AMD will be involved with GloFlo for a long time, I can easily see designs using their SOI tech for low power (&/+) low cost designs.
Mobile should be able to effectively use Big-Little CPUs.

 

[DrMrLordX]

Haven't read the article (not a paid member), but my guess is a split similar to Intel's Skylake split- a server variant and a consumer variant. Bigger SIMD units and tweaked cache sizes for server, something closer to Zen 1 for everything else.

Most servers don't need SIMD units. If there is any bifurcation (trifurcation?), I would expect it to be two-way (client/server, HPC) or three-way (client, server, HPC).

 

[maddie]

Most servers don't need SIMD units. If there is any bifurcation (trifurcation?), I would expect it to be two-way (client/server, HPC) or three-way (client, server, HPC).

Even though Zen can scale to low power usage, don't you think there's a need for an even lower power optimized core strategy? Thus client is really two seperate core designs.

 

[davidbepo]

zen is already extremely scalable i dont really see a need to differentiate

 

[Panino Manino]

I also don't see a need to differentiate, not to offer low power, Zen is already capable of doing that.

On the server side, there's really a need for AMD to do that? To compete with Intel there?

 

[ao_ika_red]

It would nice to see Puma successor.

 

[nandnandnand]

I just want regular Zen 2/2+/3, etc. clocked down to under 10 Watts, with Navi or better graphics, 4+ cores, for fanless Chromebooks (or non-Google fanless laptops, tablets). Too hot? Just lower the clock speeds.

 

[whm1974]

I just want regular Zen 2/2+/3, etc. clocked down to under 10 Watts, with Navi or better graphics, 4+ cores, for fanless Chromebooks (or non-Google fanless laptops, tablets). Too hot? Just lower the clock speeds.

How about running Linux instead of ChromeOS?

 

[nandnandnand]

How about running Linux instead of ChromeOS?

That doesn't have anything to do with what I said. You can completely erase ChromeOS and put Linux on if you want to.

 

[PotatoWithEarsOnSide]

Reducing the clocks will do very little for Zen-based power consumption. The base power consumption has a floor that is ultimately set by IF; the cores themselves draw very little power.

 

[krumme]

As I recall the wsa ends in 2024. How does amd eg. fullfill the wsa in 2023?

 

[NTMBK]

As I recall the wsa ends in 2024. How does amd eg. fullfill the wsa in 2023?

Last I saw, the revised WSA only held through 2021: https://www.anandtech.com/show/1391...th-globalfoudries-set-to-buy-wafers-till-2021

 

[Kocicak]

Differentiating cores means that one core will be used quite a long time and improvements in performance be done with adding modules with cores and trickling down the cores to lower tier products. Exactly the same core desing can start its life in highest end server part on one process and end few years later on a different process in lower end product.

 

[moinmoin]

Differentiating cores would mean different core designs used. So far the opposite extreme is true, even with Zen 2 the cores (now in form of chiplets) are still the same while server and consumer platforms are differentiated through the I/O chip (with the one for HEDT not yet confirmed). AMD didn't bother differentiating the cores at the low end with the APUs so far since the money just isn't there to make that worthwhile (yet?) so a differentiation at the top end would be more likely (like adding AVX512 support for the niches that want it?).

 

[krumme]

Last I saw, the revised WSA only held through 2021: https://www.anandtech.com/show/1391...th-globalfoudries-set-to-buy-wafers-till-2021

Yeaa. "However it also won't be the last; while the latest amendment sets purchase targets through 2021, the overall WSA itself will still run through March 1, 2024."

The current io dies and zen plus apu can probably fullfill that role fine in 19 to 21 but from there it seems to me its a bit unclear how amd should move gf capacity?

 

[Atari2600]

Look folks, its Charlie.

There will be as always, a kernel of truth (which is credit to Charlie) extrapolated into something beyond all recognition (which is anti-credit to Charlie!).


The number of times I've read Charlie say Nvidia or Intel were doomed only to find the world kept turning....


It's likely to be something as simple as slightly different manufacturing processes for desktop and for server - to go for different speed/power priorities.

 

[DrMrLordX]

Even though Zen can scale to low power usage, don't you think there's a need for an even lower power optimized core strategy? Thus client is really two seperate core designs.

They already have one. Raven Ridge/Picasso/Renoir. That's about as low-power as they're gonna get. They aren't chasing the phone/tablet sector.

On the server side, there's really a need for AMD to do that? To compete with Intel there?

Maybe, maybe not. It really depends on how much of a market there is for enhanced SIMD performance in the CPU. Intel has already bifurcated their high-performance Core design between AVX-512-capable cores and those that are not. IceLake bring some reunification that Cannonlake couldn't (because 10nm). But it remains to be seen whether it makes any sense to offer AVX-512 in a client product like IceLake. Just based on the way clockspeeds tank whenever any AVX-512 instructions are issued on any core, I'm guessing no.