Sandy Bridge is Dual core or Quad core

[cbn]

http://www.fudzilla.com/content/view/17506/1/

Will Intel's enthusiast mainboards (ie, LGA 1366) have fusion of graphics/CPU or will they continue on as discrete graphics only?

Next question, Could having the GPU on the same die as the CPU improve memory performance?

 

[Maximilian]

I read somwhere that 1366 dosent have graphics pins or somthing so it cant have cpu graphics. Dont know how true that is though.

 

[IntelUser2000]

S136x will continue on as discrete graphics card, enthusiast and workstation platform. Now compatibility with current sockets aren't guaranteed, as Sandy Bridge on the S136x socket is rumored to have PCI Express integrated. Although, I guess its possible to have it compatible so you have lanes from the CPU+lanes from X58.

News of compatibility is a LITTLE bit more positive on the S1156 platform. S1155 is physically compatible, so you might be able to just drop Sandy Bridge into the current Socket 1156 setups. According to Tech Report, the extra pin is due to integrated graphics, and we might not need that with having it on same die on Sandy Bridge.

Sandy Bridge B2-Socket 136x/6 and 8 cores
Sandy Bridge H2-Socket 1155/2 and 4 cores, 6 a possibility/Graphics on die

*snip*

Next question, Could having the GPU on the same die as the CPU improve memory performance?

It's not that having GPU on the same die as the CPU that improves memory performance. It's having memory controller on the same die that improves performance. Remember, that on Arrandale/Clarkdale, even the memory controller is on a seperate die. In theory, even Clarkdale has better memory performance than Core 2 as on package means physically less distance, and it does indeed have more memory bandwidth.

 

[IntelUser2000]

Some Sandy Bridge speculations:

Sandy Bridge B2-It is rumored to have 2.5MB L3 cache per core, so the 6 and 8 core versions would have 15 and 20MB L3 cache respectively. I believe the L2 cache will also be raised to 1MB per core.

Sandy Bridge H2-1.5MB L3 per core, which makes 3MB and 6MB for 2 and 4 core versions. I believe the L2 cache in this case will be 512KB.

In the Nehalem architecture, it uses a combination of exclusive and inclusive cache hierarchy. L1 is not inclusive with L2, but both are inclusive with L3. Physically on the 4 core Nehalem there are 9MB equivalent of SRAM on the die(4x256KB + 8MB).

In Sandy Bridge, one of the goals is to increase performance without increasing die size significantly, if at all. On the H2, it'll probably use entirely seperate L2 cache that isn't inclusive with the L3. L3 cache is usually used for snoop filtering, and isn't needed in mainstream segments(or for that matter PC). Which is why I believe H2 will have only 1.5MB L3 per core. Physically there should still be only 8MB, which is 1MB less than Nehalem.

On the B2, it'll be used for dual CPU workstations and snoop filter and cache coherency will be important, especially with number of cores increasing. Because the L2 cache size will be increasing to 1MB, L3 cache will have to increase to compensate, as its inclusive. Total physical L3 cache on die will be L2+L3, or 28MB in case of 8 core B2 and 21MB for 6 core.

None of the Sandy Bridge versions will arrive before 2011(apart from early appearances ), the upside is that unlike Nehalem, or even any of the previous Intel CPUs, the silicon is well ready and all market segments will arrive in very close timeframe, even the EX.

 

[cbn]

Some Sandy Bridge speculations:

Sandy Bridge B2-It is rumored to have 2.5MB L3 cache per core, so the 6 and 8 core versions would have 15 and 20MB L3 cache respectively. I believe the L2 cache will also be raised to 1MB per core.

Sandy Bridge H2-1.5MB L3 per core, which makes 3MB and 6MB for 2 and 4 core versions. I believe the L2 cache in this case will be 512KB.

In the Nehalem architecture, it uses a combination of exclusive and inclusive cache hierarchy. L1 is not inclusive with L2, but both are inclusive with L3. Physically on the 4 core Nehalem there are 9MB equivalent of SRAM on the die(4x256KB + 8MB).

In Sandy Bridge, one of the goals is to increase performance without increasing die size significantly, if at all. On the H2, it'll probably use entirely seperate L2 cache that isn't inclusive with the L3. L3 cache is usually used for snoop filtering, and isn't needed in mainstream segments(or for that matter PC). Which is why I believe H2 will have only 1.5MB L3 per core. Physically there should still be only 8MB, which is 1MB less than Nehalem.

On the B2, it'll be used for dual CPU workstations and snoop filter and cache coherency will be important, especially with number of cores increasing. Because the L2 cache size will be increasing to 1MB, L3 cache will have to increase to compensate, as its inclusive. Total physical L3 cache on die will be L2+L3, or 28MB in case of 8 core B2 and 21MB for 6 core.

None of the Sandy Bridge versions will arrive before 2011(apart from early appearances ), the upside is that unlike Nehalem, or even any of the previous Intel CPUs, the silicon is well ready and all market segments will arrive in very close timeframe, even the EX.

Thanks for the info. It looks like Intel is increasing the performance gap between LGA 1366 and LGA 1156/1155.