- Oct 14, 2003
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Based on the infos that are shown from IDF happening today, here are some details on Intel's next generation microarchitecture code-named Sandy Bridge.
 
CPU
-Addition of uop cache on top of what's in Nehalem
-2 load + 1store ports compared to 1 load and 1 store
-Physical Register File
-New and improved branch predictor optimized for power
-2nd load port helps on store forwarding(benefits lots of code)
-Area efficient 256-bit FP
-SHA acceleration
-faster ADC and arithmetic multiply
 
Graphics
-Larger register file
-New transcendental math capability with 4-20x more throughput
-Improvements on the ISA/branching
-CISC ISA to improve instruction throughput
-Overall each EU is 2x more capable than previous generation(
-Supports up to 4 displays independent or concurrently
-4x Multi-sampled AA(the earlier parts support 1x, so nothing)
-With AA they also added DX10.1 support
-OpenGL 3.0
-OpenCL 1.1?
 
L3 cache sharing between CPU cores, GPU cores, media and integrated memory controller
 
Ring architecture
-96GB/s per ring connection*
-384GB/s bandwidth last level cache(L3) with 4 cores, or 192GB/s with 2 cores*
-Modular for easier configuration between dies
 
*At 3GHz
 
Other
-Improved power management that will be more in line with workload
-Ability to Turbo Mode to single core frequency with all or most cores active for a brief time
			
			CPU
-Addition of uop cache on top of what's in Nehalem
-2 load + 1store ports compared to 1 load and 1 store
-Physical Register File
-New and improved branch predictor optimized for power
-2nd load port helps on store forwarding(benefits lots of code)
-Area efficient 256-bit FP
-SHA acceleration
-faster ADC and arithmetic multiply
Graphics
-Larger register file
-New transcendental math capability with 4-20x more throughput
-Improvements on the ISA/branching
-CISC ISA to improve instruction throughput
-Overall each EU is 2x more capable than previous generation(
-Supports up to 4 displays independent or concurrently
-4x Multi-sampled AA(the earlier parts support 1x, so nothing)
-With AA they also added DX10.1 support
-OpenGL 3.0
-OpenCL 1.1?
L3 cache sharing between CPU cores, GPU cores, media and integrated memory controller
Ring architecture
-96GB/s per ring connection*
-384GB/s bandwidth last level cache(L3) with 4 cores, or 192GB/s with 2 cores*
-Modular for easier configuration between dies
*At 3GHz
Other
-Improved power management that will be more in line with workload
-Ability to Turbo Mode to single core frequency with all or most cores active for a brief time
			
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