Samsung obtains world's first 450-mm tool

Idontcare

Elite Member
Oct 10, 1999
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Samsung obtains world's first 450-mm tool

The 450-mm era has finally begun, but will the next-generation wafer size move the IC and chip-equipment industries towards bankruptcy?

The proposed new and costly 450-mm fabs are a huge gamble and could indeed make or break the industry. In any event, Japan's S.E.S. Co. Ltd. has reportedly just shipped the world's first 450-mm tool--a next-generation wafer cleaning system, according to sources. The first 450-mm tool, which is said to be a R&D prototype, is reportedly going to South Korea's Samsung Electronics Co. Ltd., according to sources.

http://www.eetimes.com/news/se...VN?articleID=208402622

Pretty exciting to see things moving and shaking in the 450mm toolset industry.

I personally would have expected this day to not come for another 3-4 years, Samsung is obviously making a statement here by (1) ensuring they are at the forefront of the 450mm transition, and (2) ensuring the rest-of-the-world knows they are at the forefront of the 450mm transition. (it is rare for an IDM to publicly acknowledge tool shipments from specific vendors, usually this is considered trade secret material and competitive info)
 

nyker96

Diamond Member
Apr 19, 2005
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if this is wafer size that it's way bigger than the current 300. Hey they will make more money if they can get this to work.
 

Cookie Monster

Diamond Member
May 7, 2005
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Wow. I thought this stuff wouldnt happen til 2~3 years from now. What a bold move by Samsung (i mean just imagine the costs/risks involved in transitioning to the 450mm tools), but im not as surprised by the move taken by the second biggest semi conductor company in the world.

Wonder what the other companies has to say about this rather exciting news.
 

firewolfsm

Golden Member
Oct 16, 2005
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The day you all "thought wouldn't come for 2-4 years" still hasn't come. We aren't anywhere NEAR even starting the transition. If anyone here was around for the transition to 300mm they'd know that. This is the start of a slow process, it's only the early pressure on companies to begin investments.
 

Idontcare

Elite Member
Oct 10, 1999
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Originally posted by: firewolfsm
The day you all "thought wouldn't come for 2-4 years" still hasn't come. We aren't anywhere NEAR even starting the transition. If anyone here was around for the transition to 300mm they'd know that. This is the start of a slow process, it's only the early pressure on companies to begin investments.

:confused: Oh how I love those posters who have a tiny bit knowledge thanks to Wiki and proceed to go on posting rampages as if they actually work in the industry.

Having personally been involved at the hands-on fab level in the transition from 6" to 8" as well as 8" to 12" I know exactly what I meant by my statement.

This is a milestone in what has always been a 5 yr transition timeline for every wafer transition that has come before. It is also a very crucial milestone at that, which is why I posted of it here for others to be remined that the wheels are still turning.

I am quite excited to see the industry reach this point in the transition 4-5 years sooner than I was otherwise expecting, it means we are likely to get to the end of the transition 4-5 years sooner than I was expecting as well (2013 timeframe versus 2018).
 

VirtualLarry

No Lifer
Aug 25, 2001
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As the wafers get bigger, isn't the delta between the "good" and "poor" chips on the wafer going to increase? Meaning that you still only get so many prime chips at the center of the wafer, and then you get more of the mediocre chips near the outside of the wafer?
 

magreen

Golden Member
Dec 27, 2006
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Wow, this is truly exciting news!

Er, actually I have absolutely no idea what any of this thread is talking about. Is this a larger wafer or smaller? Why is a larger/smaller wafer good? Is there creme filling between wafers?
 

BrownTown

Diamond Member
Dec 1, 2005
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Originally posted by: VirtualLarry
As the wafers get bigger, isn't the delta between the "good" and "poor" chips on the wafer going to increase? Meaning that you still only get so many prime chips at the center of the wafer, and then you get more of the mediocre chips near the outside of the wafer?

Thats one of the possible problems, but I guess the idea is that you don't tranisition to larger wafers until you can get uniform enough characteristics that the whole wafer is acceptable.
 

Lonyo

Lifer
Aug 10, 2002
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Originally posted by: Idontcare
Originally posted by: firewolfsm
The day you all "thought wouldn't come for 2-4 years" still hasn't come. We aren't anywhere NEAR even starting the transition. If anyone here was around for the transition to 300mm they'd know that. This is the start of a slow process, it's only the early pressure on companies to begin investments.

:confused: Oh how I love those posters who have a tiny bit knowledge thanks to Wiki and proceed to go on posting rampages as if they actually work in the industry.

Having personally been involved at the hands-on fab level in the transition from 6" to 8" as well as 8" to 12" I know exactly what I meant by my statement.

This is a milestone in what has always been a 5 yr transition timeline for every wafer transition that has come before. It is also a very crucial milestone at that, which is why I posted of it here for others to be remined that the wheels are still turning.

I am quite excited to see the industry reach this point in the transition 4-5 years sooner than I was otherwise expecting, it means we are likely to get to the end of the transition 4-5 years sooner than I was expecting as well (2013 timeframe versus 2018).
So are you talking transition meaning most new fabs will be 450mm, or transition as in a few companies will start building 450mm fabs?
Because Intel seem to have about a 50/50 split with 200mm/300mm fabs even now (from their website), although all the new ones are 300mm.
So are you saying in ~5 years most new fabs (at least from the large companies) will be 450mm?
 

Phynaz

Lifer
Mar 13, 2006
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Originally posted by: VirtualLarry
As the wafers get bigger, isn't the delta between the "good" and "poor" chips on the wafer going to increase? Meaning that you still only get so many prime chips at the center of the wafer, and then you get more of the mediocre chips near the outside of the wafer?

It's absolute myth that the chips in the center of a wafer are somehow "better" than the chips further out from the center.

Think about it, what could possibly cause this to occur?

 

pm

Elite Member Mobile Devices
Jan 25, 2000
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To the best of knowledge (which, I'd admit mostly comes from reading magazines like the EETimes), the timeline to the 450mm transition has not been moved up. It is still planned for a 2012 pilot line (a complete set of tools for 450mm available) with volume production at a later date. This would be consistent with the typical decade-cadence for wafer size transistions...


It's also worth noting that several industry leaders have said relatively recently that 450mm will not happen for a long, long time. Mike Splinter (my former VP, now CEO of Applied Materials ), Rick Hill (CEO of Novellus), and others have said fairly recently that 450mm is more than a decade off (from 2006/2007 when they spoke)... which would mean that the wafer cadence would miss a beat, or at least half a beat.

When did the voume 300mm transition occur? 2004-ish?

Also, it has been my understanding that the 450mm transition will be lead by a combination of Intel, Samung and TSMC. I don't think that Samsung is tryig to lead it alone - even if they seem to have gotten off to an earlier start.

It's absolute myth that the chips in the center of a wafer are somehow "better" than the chips further out from the center.

It has a basis in reality. The ones of the edge of the wafer often had (and still do to a lesser extent) the highest defect rates. This has to do with an increase in dislocations and other crystalline defects caused by jarring/bumps/gravity while the wafer was transported edge-up (perpendicular to the ground) in a wafer carrier, as well as other issues caused by the wafer handler, and also the way that pattern lithography works with steppers.

I've also seen a lot of wafers - particularly several process generations ago (not so much recently) where the fastest parts are in the center of the wafer, the slowest to the outside. Like this: http://images.pennnet.com/arti...611mlw_improving04.gif I'm not entirely sure why this occurs - although I'd guess that it's a problem with the lithography light source and optics... basically that you are taking a point light source and then trying to make it into a vertically oriented source and there are optical problems near the edges... but like I said, I'm not totally sure.
 

Idontcare

Elite Member
Oct 10, 1999
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Originally posted by: Lonyo
So are you talking transition meaning most new fabs will be 450mm, or transition as in a few companies will start building 450mm fabs?
Because Intel seem to have about a 50/50 split with 200mm/300mm fabs even now (from their website), although all the new ones are 300mm.
So are you saying in ~5 years most new fabs (at least from the large companies) will be 450mm?

Historically a new wafer-size "era" is considered to be officially "upon us" when the third fab has its first wafers exit the fab. This is not a hard rule of thumb but its well accepted.

It's also the same rule of thumb for ascribing when the industry can be considered to have truly entered production phase for the newest technology node (i.e. the logic CMOS industry won't be considered as being "in 45nm" until the third IDM is actually shipping 45nm node product)

You can't go by the ratio's of leading-edge wafer size fabs built versus trailing edge, that isn't the point in ascribing something as a transition. 450mm isn't about 300mm going away, its about the industry having yet one more option available to itself for maximizing ROI for certain economies of scale businesses.

200mm fabs are still built today and for good reason. When the first 600mm fabs are being built in 20 yrs they will still be building 300mm fabs for the lower volume guys.

Having been in the industry myself for as much as I saw I really did not expect the first 450mm toolset to change hands from vendor to IDM for at least another 4 years. I don't pay attention to what the published timelines are in mainstream media as they are notoriously full of BS. I wait for the data to slowly trickle out as then I know precisely where they are on the fairly generic timeline for how these things are managed (marketing hype and PR BS aside).
 

Idontcare

Elite Member
Oct 10, 1999
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Originally posted by: Acanthus
Samsung is one of the worlds largest wafer consumers. Im not suprised at all they want to be on the forefront of this.

Exactly my thinking too. Samsung is making HUGE inroads into the foundry business segment.

Samsung posts 413 percent growth in foundry revenues

It may have been a lacklustre year in 2007 for revenue growth on the parts of TSMC, UMC and Chartered Semiconductor, but according to figures released by IC Insights, Samsung Electronics experienced foundry revenue growth of 413 percent in 2007 compared to 2006 and became the 10th largest foundry by sales.

Samsung not only outstripped revenue growth of pure-play foundries but also that of other IDMs that operate foundry services such as long-term player IBM.

http://www.fabtech.org/content/view/6416/

These guys aren't playing around, you can bet TSMC is looking nervously in the rear-view mirror right now.
 

Extelleron

Diamond Member
Dec 26, 2005
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This is definitely a big move, I'm pretty surprised Intel wouldn't be the first to purchase 450mm tools though.

I'm not sure how eager the industry is going to be to go to 450mm though. For companies like Samsung and Intel, bigger wafers make sense, but I'm not sure it will be the same for everyone. Unless things have changed, it sounded to me like a lot of companies were not eager to jump to 18-inch wafers and wanted to make best use of their 300mm investments. As I said, the big companies like Samsung, Intel, and probably TSMC will be interested in this.... but smaller companies like AMD are not going to be. In the case of AMD they definitely don't need more production resources.

 

uclaLabrat

Diamond Member
Aug 2, 2007
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Originally posted by: Phynaz
Originally posted by: VirtualLarry
As the wafers get bigger, isn't the delta between the "good" and "poor" chips on the wafer going to increase? Meaning that you still only get so many prime chips at the center of the wafer, and then you get more of the mediocre chips near the outside of the wafer?

It's absolute myth that the chips in the center of a wafer are somehow "better" than the chips further out from the center.

Think about it, what could possibly cause this to occur?

Slower recrystallization of the silicon at the center? The wafer takes bulk silicon and recrystallizes it to form the wafer, right?
 

Idontcare

Elite Member
Oct 10, 1999
21,110
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Originally posted by: Phynaz
Originally posted by: VirtualLarry
As the wafers get bigger, isn't the delta between the "good" and "poor" chips on the wafer going to increase? Meaning that you still only get so many prime chips at the center of the wafer, and then you get more of the mediocre chips near the outside of the wafer?

It's absolute myth that the chips in the center of a wafer are somehow "better" than the chips further out from the center.

Think about it, what could possibly cause this to occur?

There is one fundamental reason why center-to-edge non-unformities exist and it has to do with pressure differentials across the wafer surface in all sub-atmospheric processing steps in which mass transport is a key component of the intended processing.

Your sub-atmospheric deposition processes, your sub-atmospheric plasma etching and ashing processes for examples.

Because the chamber exhaust ports must be at the edge of the wafer (or beyond) all reactants and products from the center of the wafer are afforded additional interaction time with the regions of the wafer that exist between the center of the wafer and the edge of the wafer.

This phenomenon also exists in atmospheric processing steps which are single-wafer (versus batch processing) in which reactant and byproduct concentration gradients are unavoidable during processing...such as single-wafer cleans as well as Cu ECD.

You can think of it as density fluctuations, mass gradients, or pressure gradients, they are in effect all manifestations of the same phenomenon but described by a different sect of science.

The magnitude of the gradient effect can be minimized (or exaggerated if desired, corrective CMP for instance is intentionally engineered to counter the center-to-edge depth profile from Cu ECD) by improvements in hardware design (showerhead designs in plasma chambers for example) and improvements in processing sequencing (rastering a dispense nozzle across a wafer instead of residing in fixed radial position).

This merely speaks to why having a center-to-edge distribution is unavoidable...whether the effect of this unavoidable cause results in "better" chips at the wafer center or the wafer edge or the wafer mid-radius (called the "golden donut" believe it or not) all comes down to the process integration and yield enhancement teams desire to have certain parametrics optimized in the center or edge of the wafer.

The cause of center-to-edge wafer variation does not pre-ordain the effect of having good chips from the wafer center, it merely explains why you can have good chips at the center and laggardly chips at the edge. The reverse effect can occur for the same cause.
 

Phynaz

Lifer
Mar 13, 2006
10,140
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It has a basis in reality. The ones of the edge of the wafer often had (and still do to a lesser extent) the highest defect rates.

He said chip quality, not yield.

I'm assuming he is refering to the myth that a chip from the center of the wafer is a better clocker.

I suppose this may have been true at one time in the past when the entire wafer was exposed at once during processing. I could see where the "focus" could be calibrated to the center of the wafer.