"The 512Mb Double-Data-Rate-II (DDR-II) SDRAMs are high-speed CMOS 512Mb Double Data Rate II Synchronous DRAM devices. The 512Mb chip is organized as either 32Mbit x 4 I/O x 4 banks or 16Mbit x 8 I/O x 4banks or 8Mbit x 16I/O x 4 banks device. This synchronous device achieve high speed double-data-rate transfer rates of up to 533Mb/sec/pin (DDR533) for general applications.
The chip is designed to comply with the following key DDR-II DRAM features: (1) posted CAS with additive latency, (2) write latency = read latency -1 , (3) Off-Chip Driver(OCD) impedance adjustment, (4) On Die Termination.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with DQS in a source synchronous fashion. A fourteen bit address bus is used to convey row, column, and bank address information in a RAS/CAS multiplexing style. For example, 512Mb(x4) device receive 14/11/2 addressing.
The 512Mb DDR-II devices operate with a single 1.8V¡¾0.1V power supply and 1.8V ¡¾ 0.1V VDDQ. The 512Mb DDR-II devices are available in 60ball FBGAs(x4/8) and available in 84ball FBGAs(x16). Auto Refresh (CBR) and Self Refresh operations of 8192refresh cycles per 64ms are supported. (Refresh Period 7.8us)"
Good find. Looks like it's still a way off hough, it lists them as Engineering Samples with a date of Nov '02. I like the DDR533 though...looks nice..
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