[S|A] Broadwell supply a "trickle" until 2015

[mikk]

Release time schedule could make sense too, RTS is Intels release window.

 

[ancientarcher]

http://www.reuters.com/article/2014/05/18/us-intel-chips-idUSBREA4H08P20140518

""I can guarantee for holiday, and not at the last second of holiday," Krzanich said in an interview. "Back to school - that's a tight one. Back to school you have to really have it on-shelf in July, August. That's going to be tough."

I don't consider October and certainly not December "tight".


1) Skylake's pull-in to Q2'15; 2 years after Broadwell, when you extrapolate Cannonlake is Q2'16

2) 14nm (and 10nm too) is projected to last exactly 2 years.

Intel doesn't see any major difficulties in the coming 10 years.

Interesting that Intel won't talk about double patterning here in the chart. Intel 22nm trigate was still single patterning while 20nm for the foundries is double patterning. So basically, Intel and the foundries are about par (maybe the foundries are a bit ahead) on that.

I am also wondering how much of Intel's troubles with 14nm delays are due to its aggressive tightening of transistors and metal/poly pitch for this generation. It sure looks good on a chart when comparing vs TSMC, but they are trying to do two node jumps in one. Tough! They might just have shot themselves in the foot trying to bite too much. Maybe they should have been conservative and not tried to so aggressively outmatch TSMC on area.

 

[Homeles]

Huh? Intel's been using double patterning since 65nm. They chose to adopt double patterning before they adopted immersion lithography, which they used at 32nm.

 

[ancientarcher]

Huh? Intel's been using double patterning since 65nm. They chose to adopt double patterning before they adopted immersion lithography, which they used at 32nm.

Seriously??
How can that be cost effective? Can anyone else confirm it?

 

[Pheesh]

Yes but: https://www.zauba.com/import-broadwell-hs-code.html

I'm not sure this proves anything except that engineering samples of Cherry Trail and Broadwell are flying around.

Cool site

https://www.zauba.com/import-skylake-hs-code.html

 

[pw257008]

This basically sums up your whole post, you're milking Intel's 14nm yield issues to try to make your point. Everything suggests a release of 10nm in mid-2016, and you reply that they could have problems, like 14nm. Quite obvious, isn't it?

But those are just that: unforeseen problems. I don't see why I should take nonexistent problems into account.

Like civil war and ethnic cleansing between the Sunnis and Shias in Iraq was an unforeseen problem circa 2002. You should always take into account the known unknowns and unknown unknowns, as best as you can. Especially if you're predicting on a message board.

 

[witeken]

I am also wondering how much of Intel's troubles with 14nm delays are due to its aggressive tightening of transistors and metal/poly pitch for this generation. It sure looks good on a chart when comparing vs TSMC, but they are trying to do two node jumps in one. Tough! They might just have shot themselves in the foot trying to bite too much. Maybe they should have been conservative and not tried to so aggressively outmatch TSMC on area.

It's about a 2.2x density improvement, not too much more than 2x. I think the technologies that Intel used were simply necessary to get a meaningful improvement and Intel simply decided to take the technology as far as it can go.

 

[witeken]

Huh? Intel's been using double patterning since 65nm. They chose to adopt double patterning before they adopted immersion lithography, which they used at 32nm.

Correct me if I'm wrong, but for some things you need double patterning, and for others Intel could still use single patterning in 22nm.

 

[Khato]

Correct me if I'm wrong, but for some things you need double patterning, and for others Intel could still use single patterning in 22nm.

Correct. Though they've been selectively using double patterning for awhile.

Page 37 - http://download.intel.com/pressroom/kits/advancedtech/pdfs/VLSI_45nm_HiKMG-presentation.pdf

Near the end - http://www.eetimes.com/document.asp?doc_id=1281203 - it's mentioned that double patterning is "used for the sacrificial polysilicon layer."

 

[Homeles]

Seriously??
How can that be cost effective? Can anyone else confirm it?

Intel adopted double patterning first for a number of reasons. First, you don't have to buy new equipment, unlike immersion litho. I think you still have to buy more scanners to mitigate the volume hit, but at that point dry scanners were "old equipment" and would be less expensive than fancy new immersion scanners. It's also relatively trivial for them to make new masks. You know there's something like 8 different configurations for Haswell alone?

It's still expensive to make masks of course, but they don't have to cater to many customers, and didn't have to cater to any back when they made that decision. It made more sense for TSMC to put it off as long as possible, because they have customers that would keel over and die if they had to create extra masks to pattern the critical bits, as those customers don't have anywhere near the volume for a single design that Intel would have.

Idontcare actually claims that TSMC is the one to thank for making immersion litho viable.

Lithography is just one of the steps involved in processing a wafer, and doubling the cost of lithography does not double the total cost of fabrication. You actually don't even "double" lithography costs by going to double patterning anyway, as you're only doing the parts that need it. These two reasons, primarily the first one, is why it still makes economic sense.

Look at this chart for instance. The other steps stay mostly flat. Litho doubles from 28 to 20nm, but is less than double from 20nm to 14nm.

All the meanwhile, you're still patterning twice as many structures in a given space, meaning your economics are improving. And GloFo's citing IMEC here, not their own process, so the 14nm BEOL nonsense doesn't apply here.

Correct me if I'm wrong, but for some things you need double patterning, and for others Intel could still use single patterning in 22nm.

Right. You don't need to do double patterning on metal layer 9, for instance.

 

[carop]

Idontcare actually claims that TSMC is the one to thank for making immersion litho viable.

Burn J. Lin of TSMC invented immersion lithography. Over the course of his career he has received several awards:

Burn J. Lin, TSMC’s Vice President of Research and Development, has been awarded the 2013 IEEE Jun-ichi Nishizawa Medal for outstanding contributions to material and device science and technology for his invention of immersion lithography.

http://www.forbes.com/sites/jimhandy/2013/06/26/father-of-immersion-litho-receives-award/

Lithography is just one of the steps involved in processing a wafer, and doubling the cost of lithography does not double the total cost of fabrication. You actually don't even "double" lithography costs by going to double patterning anyway, as you're only doing the parts that need it. These two reasons, primarily the first one, is why it still makes economic sense.

According to Geoffrey Yeap of Qualcomm BEOL accounts for 45% - 50% of the total cost at the (foundry) 20nm and 16nm nodes, and will account for more than 50% of the cost at the (foundry) 10nm node:

http://www.eetimes.com/author.asp?section_id=36&doc_id=1321650

(On the foundry side) double pattering technology is always used to refer to the printing the tightest metal pitches. So, Intel 22nm node does not have double patterning technology since it is using a 90nm metal 1 pitch.

Furthermore, there are different double patterning techniques (LELE, SADP) having different process costs. The following slide is from ASML:

I believe Intel is using Self Aligned Double Patterning (SADP) at its 14nm node. However, Intel has not released the specifications of its 14nm node yet.

I have not ruled out the possibility that Intel will not do a proper release of the process or device specifications of its 14nm node. The specs are not in a hurry though. They can wait until 14nm parts are spotted in the wild so as to be reverse-engineered (RE). RE is protected in the US by the Semiconductor Chip Protection Act. There is similar legislation in Japan, the European Union, and other jurisdictions.

 

[NostaSeronx]

Samsung's 14-nm FinFETs use LELE. With 10-nm using SADP.

IBM's SOI FinFETs on 14-nm use SADP. 10-nm maybe SAQP?

 

[Phynaz]

Huh? Intel's been using double patterning since 65nm. They chose to adopt double patterning before they adopted immersion lithography, which they used at 32nm.

Actually it was at 45nm that Intel started using double patterning

Intel adopted it for critical areas at 45nm, when the rest of the industry was pushing immersion lithography. Then, at 32nm, TSMC and GlobalFoundries began using some double patterning, while Intel went with immersion lithography.

http://www.extremetech.com/computin...hography-technique-to-push-moores-law-to-20nm

 

[Homeles]

Yeah, Wikipedia made that claim, and had a couple of sources, which were dead links. 45nm used it for certain, though.

 

[bullzz]

http://semiaccurate.com/2014/07/11/intel-castrates-broadwell-gutting-performance/

may be this explains the F step? release a SKU to push products out while spending more time on optimization

 

[mikk]

http://semiaccurate.com/2014/07/11/intel-castrates-broadwell-gutting-performance/

may be this explains the F step? release a SKU to push products out while spending more time on optimization

What exactly? Charlie is dumb, he may refer to the low clockspeeds of Broadwell-M while ignoring the low TDP.

 

[DrMrLordX]

Like civil war and ethnic cleansing between the Sunnis and Shias in Iraq was an unforeseen problem circa 2002. You should always take into account the known unknowns and unknown unknowns, as best as you can. Especially if you're predicting on a message board.

Gin Rummy: I always say the absence of evidence is not the evidence of absence.
Riley: What?
Gin Rummy: Simply because you don't have evidence that something does exist does not mean you have evidence of something that doesn't exist.
Riley: What?
Gin Rummy: What country are you from?
Riley: What?
Gin Rummy: 'What' ain't no country I ever heard of! They speak English in 'What'?
Riley: What?
Gin Rummy: English, motherf*****! Do you speak it?
Riley: Yeah.
Gin Rummy: So you understand the words I'm saying to you!
Riley: Yeah.
Gin Rummy: Well, what I'm saying is that there are known knowns and that there are known unknowns. But there are also unknown unknowns; things we don't know that we don't know.
Riley: What?
Gin Rummy: Say what again! Say what again! I dare you! I double dare you, motherf*****! Say what one more time!