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[RWT] Tile-based Rasterization in Nvidia GPUs

Do you think they licensed this tech from Imagination or is this different enough from the PowerVR implementation of hardware based deferred and tile rending that it does not infringe?
 
imported_bman said:
Do you think they licensed this tech from Imagination or is this different enough from the PowerVR implementation of hardware based deferred and tile rending that it does not infringe?
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Probably just improved upon the Tile Based Rasterization (TBR) that 3Dfx were doing and Gigapixel (bought by 3Dfx) before that. Nvidia probably has a fair few TBR patents of their own.

It's been a long time coming though: https://forum.beyond3d.com/threads/nv-now-owns-tile-based-rendering-technology.10317/
 
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It probably infringes something somewhere, but in the article it also says 3dfx aquired a company that made a tile based rasterization gpu, and 3dfx got bought by nvidia.

I don't think imagination "owns" tile based rasterization.
 
Well this explains why Maxwell was every bit as big of a jump in perf/w over Kepler on the same node as Pascal was over Maxwell, despite being on a new node.

With this info, it's now a likely scenario that Volta on the same node as Pascal won't be the same jump that Maxwell was, I.e. instead of GV104 being 50-60% faster than GP104 at release (like how GM204 vs. GK104 was) it'll probably be closer to 30-40%.
 
Flapdrol1337 said:
It probably infringes something somewhere, but in the article it also says 3dfx aquired a company that made a tile based rasterization gpu, and 3dfx got bought by nvidia.

I don't think imagination "owns" tile based rasterization.
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Everyone has tested tiled rendering in at least some form at some point. AMD bought Bitboys, who then ended up working for Qualcomm making the Adreno TBIM GPU, nVidia bought gigapixel TBDR IP through 3dfx, ARM Holdings has the Mali GPU that does TBIM, Intel Larrabee was supposed to be TBDR, PowerVR and Broadcom GPUs are TBDR.

Tiled rendering is not directly better or worse than direct rendering. It's different. It has both great advantages (reduction of bandwidth use, reduction of work at PS stage), and great disadvantages (either greatly amplifying amount of work needed at the VS stage or large internal storage).

Since we have not read stories about how Maxwell sucks at large geometry sets, nVidia has somehow learned how to mitigate the disadvantages. Hats off to them.
 
Tuna-Fish said:
Everyone has tested tiled rendering in at least some form at some point. AMD bought Bitboys, who then ended up working for Qualcomm making the Adreno TBIM GPU, nVidia bought gigapixel TBDR IP through 3dfx, ARM Holdings has the Mali GPU that does TBIM, Intel Larrabee was supposed to be TBDR, PowerVR and Broadcom GPUs are TBDR.

Tiled rendering is not directly better or worse than direct rendering. It's different. It has both great advantages (reduction of bandwidth use, reduction of work at PS stage), and great disadvantages (either greatly amplifying amount of work needed at the VS stage or large internal storage).

Since we have not read stories about how Maxwell sucks at large geometry sets, nVidia has somehow learned how to mitigate the disadvantages. Hats off to them.
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Wasn't the X360 doing something like this due to the eDRAM? Being so small and wanting to take advantage of it.
 
tviceman said:
That doesn't make sense; GM107 is just as efficient in perf/w as GM204. If GM107 was using Kepler's rendering techniques it wouldn't have the efficiency leap.
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That's only true if we assume that this tile based rendering setup is indeed the source of Maxwell's efficiency increases, but we don't actually know that for certain.

Edit: Just noticed that David Kanter edited his original comment about GM10X. He now appears to agree that GM10X probably also uses tile based rendering. http://www.realworldtech.com/forum/?threadid=159876&curpostid=159895
 
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Rezist said:
Wasn't the X360 doing something like this due to the eDRAM? Being so small and wanting to take advantage of it.
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Both Xbox One and Xbox 360 using a tiled rendering scheme. However this is completely SW driven and scene based (and not on the primitive level like this thread is about).

Background is, that not all render targets fit into eDRAM/eSRAM at the same time. So you render the whole scene for tiled buffers. When one tile is done, it is commited to main memory and the next tile is started. This way you take full advantage of bandwidth while not limited at eSRAM size even for higher resolutions.
 
I think that this is very intesting and explains several of the differences between recent nVidia GPUs and their older products / the competition. For example, tile-based rendering is very bandwidth efficient, and Maxwell/Pascal cards seem to have way too low memory bandwidth per shader relative to previous GPUs. This now can be explained as most of the rasterization work being done in cache with TBR so the raster portion uses almost no bandwidth which frees it up for other uses. Also, there is a chance that the fragments which are rasterized first are submitted to the pixel shaders before the other tiles are done - which is why nVidia may gain less from async compute because some of its geometry work and shader work already overlap.
 
some saying this is not tile based rendering in the comments on that article. Other people show similar results with larger tiles on hawaii GPUs.
 
Azix said:
some saying this is not tile based rendering in the comments on that article. Other people show similar results with larger tiles on hawaii GPUs.
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As far as I can tell, the argument in question was that this was not tile based rendering in the traditional sense (tiling of the screen), but rather just triangle tiling which looked like screen tiling due to the rather huge triangles.

Another user then modified the program to produce a bunch of smaller triangles across the screen to avoid this issue, but he still saw basically the same pattern (i.e. tiled rendering that was governed by screen location and not triangle location).
 
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