Question RTX 4000/RX 7000 price speculation thread

[moonbogg]

My prediction: The entire generation will be 2-3X msrp on ebay and at retailers. RTX 3000 series will be sold along side the 4000 series because only a few will be buying RTX 4000 series who are willing to pay $1500 for what should be a $300 RTX 4060. Not enough supply to meet demand by a long shot, pricing will be through the Oort cloud. PC gaming is dead. Your thoughts?

 

[xpea]

When Battlemage releases the order in performance hierarchy should be this: 1) AMD, 2) Intel, 3) Nvidia.

Battlemage will arrive at the end of Ada/RDNA3 cycle so it may get the crown if all stars align perfectly for intel. But Nvidia already booked TSMC N3X (HPC variant of N3) and will be much more aggressive going forward in getting new nodes. With 3 players in the arena and intense competition, next years will be interesting (again)

The thing that people can definitively forget is affordable GPUs as TSMC EUV wafers cost one arm, one leg and a kidney

 

[Aapje]

I don't believe it one second. Except for the halo AD102 SKU that will push everything to 11 to get the crown vs Navi31 (or close to it), Ada will be more efficient across the range. Fact: Monolith always win in efficiency if everything else is equal. ALWAYS.

Navi33 is monolithic, so your argument is invalid for that tier. Secondly, you are simply assuming that AD104 won't be OC'ed to the moon, even though Nvidia might need to do that to have a competing product in the middle tier. Pushing chips to very high frequencies is very inefficient, so it's extremely plausible that a multi-die design with more reasonable clocks is more efficient than a monolithic die OC'ed to the moon.

MCM interconnects have been getting more power efficient and larger caches per die have been found to greatly reduce the amount of communication between dies and thus the extra power draw that the interconnect uses. Ironically, you can read this in a paper by Nvidia.

 

[xpea]

Navi33 is monolithic, so your argument is invalid for that tier. Secondly, you are simply assuming that AD104 won't be OC'ed to the moon, even though Nvidia might need to do that to have a competing product in the middle tier. Pushing chips to very high frequencies is very inefficient, so it's extremely plausible that a multi-die design with more reasonable clocks is more efficient than a monolithic die OC'ed to the moon.

MCM interconnects have been getting more power efficient and larger caches per die have been found to greatly reduce the amount of communication between dies and thus the extra power draw that the interconnect uses. Ironically, you can read this in a paper by Nvidia.

Sorry, everything you said don't change the fact that monolithic is ALWAYS more efficient than a multi-die for the same circuit.
You argue about different design choice (large L3 cache) and SKUs competitiveness which were not my point.
The 2 Nvidia papers prove exactly what I said. You loose around 10% efficiency when going MCM.

 

[Glo.]

I don't believe it one second. Except for the halo AD102 SKU that will push everything to 11 to get the crown vs Navi31 (or close to it), Ada will be more efficient across the range. Fact: Monolith always win in efficiency if everything else is equal. ALWAYS.

It won't be more efficient. It is from software side - the same, exact architecture as Ampere, only with increased clocks, and higher SM counts.

Larger L2 cache does not do anything for the IPC of the GPUs front end, increases only memory efficiency, and allows them to reduce the VRAM needs to feed the GPU.

Smaller GPUs(107 and 106) are made on 6 nm process to save costs, rightfully, but it will come at a cost of high power draw. Don't expect less than 150W of power draw on desktop for 107 die.

And I am writing this as a person for whom AD107 is most exciting GPU die from Nvidia in years, from technical point of view.

Wait, what...

*looks at date, confirms that it isn't April 1st*

... are you smoking?

Intel having a GPU that is more performant than Nvidia when Battlemage releases? Please tell me you are joking. I highly doubt that Intel will catch up to Nvidia in just two generations. It's going to take AMD three generations of RDNA just to take the crown (at least that's what rumors suggest), so why would it take even less for Intel?

Yes, I am 100% serious.

 

[VirtualLarry]

Fact: Monolith always win in efficiency if everything else is equal. ALWAYS.

LOL.

 

[Aapje]

Sorry, everything you said don't change the fact that monolithic is ALWAYS more efficient than a multi-die for the same circuit.
You argue about different design choice (large L3 cache) and SKUs competitiveness which were not my point.
The 2 Nvidia papers prove exactly what I said. You loose around 10% efficiency when going MCM.

What you are missing is that these companies are not competing for the most efficient product, but for the best performance for the price. It's very easy to tell that the market is not very concerned with efficiency, given that the GPU's are often sold with overclocks and very conservative voltages & can be made much more efficient with some undervolting and underclocking.

It's perfectly possible for an MCM design to achieve better efficiency at a specific level of performance. In fact, that's what Nvidia's paper is arguing: that it's more efficient to achieve high levels of performance at relatively low cost with MCM than with a monolith, if you design the MCM in a smart way.

A sport like F1 is increasingly concerned about fuel efficiency, yet their cars don't look like those that compete in the Shell Eco-marathon and definitely aren't driven like the cars in that competition. That's because efficiency isn't the sole or main interest of F1, but performance. So you can't argue that the most efficient car would be the best car for F1, just like you can't argue that the most efficient GPU chip is the best for the GPU market.

 

[xpea]

To clarify, MCM makes sense only when you have to go above the reticle limit to reach a performance target and/or when yields are not good enough.
But we are talking about ultra mature TSMC 5N process that has a stellar D0 of 0.07 !!! So yields are not an issue for consumer GPUs ; not even for AD102 ~600mm2 die and even less a problem with ~380mm2 AD104 that can further be salvaged with cut-down SKUs...

PS: I also believe that N31 with the rumored 2x450mm2 GDC will beat AD102 in pure raster gaming (not so sure in RT), it's not the question. I'm more interested by Navi 32 and 33 vs their Nvidia counterparts

 

[biostud]

Isn't the main reason for going MCM to have good yield rates, to keep production costs down?

 

[Glo.]

Isn't the main reason for going MCM to have good yield rates, to keep production costs down?

Yep. On smaller nodes monolithic is much less financially feasible than chiplet, because you cannot simplify the deisgn, and scale it.

With chiplets/MCM - you design 1-2 dies that you need to yield. With monolithic, for each performance tier you need different die.

 

[xpea]

Yep. On smaller nodes monolithic is much less financially feasible than chiplet, because you cannot simplify the deisgn, and scale it.

With chiplets/MCM - you design 1-2 dies that you need to yield. With monolithic, for each performance tier you need different die.

But this is not what the rumors say. Navi31 and Navi32 have different GDC and different IO dies. Total of 4 dies. How is it better than AD102-103-104 (3dies) to cover the same market?

Edit: Don't get me wrong, MCM is the future to increase performance beyond Moore's law. it males totally sense when you need more transistors than the reticule limit. Regarding cost savings, well the true is that Navi31 is more expensive than AD102. When we will have something like AMD CPUs, ie 4~8 CCX dies and one IO die per SKU, then it will fill the MCM purpose

 

[Aapje]

So yields are not an issue for consumer GPUs ; not even for AD102 ~600mm2 die and even less a problem with ~380mm2 AD104 that can further be salvaged with cut-down SKUs...

PS: I also believe that N31 with the rumored 2x450mm2 GDC will beat AD102 in pure raster gaming (not so sure in RT), it's not the question. I'm more interested by Navi 32 and 33 vs their Nvidia counterparts

Sure, but why is AD102 a 'mere' 600 mm2 and not 900 mm2 to match the real estate of the N31? There is a limit with monolithic designs.

I do expect MCM to become much more of an advantage in the future when packaging improves further and we get processes with worse yields. My interpretation of Intel's Zettascale plans is that they expect huge gains in packaging/interconnects.

But we are talking about ultra mature TSMC 5N process that has a stellar D0 of 0.07

True, but Intel and Samsung are/were not doing so great on yields. We now pay huge markups in large part due to shortages in silicon production. So Intel and Samsung may actually have the most to gain from MCM, to reduce the impact of their lower yields, which in turn can mean better prices for consumers.

 

[Glo.]

But this is not what the rumors say. Navi31 and Navi32 have different GDC and different IO dies. Total of 4 dies. How is it better than AD102-103-104 (3dies) to cover the same market?

Edit: Don't get me wrong, MCM is the future to increase performance beyond Moore's law. it males totally sense when you need more transistors than the reticule limit. Regarding cost savings, well the true is that Navi31 is more expensive than AD102. When we will have something like AMD CPUs, ie 4~8 CCX dies and one IO die per SKU, then it will fill the MCM purpose

The die sizes are smaller, overall, for AMD chiplets, which means you get more dies per wafer. That is the whole point of going chiplet. Its easier to get plenty of 350 mm2 dies from one wafer, than it is to get one large 700 mm2, that you have to sell then to customers.

Thats the main difference.

 

[Krteq]

But this is not what the rumors say. Navi31 and Navi32 have different GDC and different IO dies...

Which rumors stated that?

 

[maddie]

Sorry, everything you said don't change the fact that monolithic is ALWAYS more efficient than a multi-die for the same circuit.
You argue about different design choice (large L3 cache) and SKUs competitiveness which were not my point.
The 2 Nvidia papers prove exactly what I said. You loose around 10% efficiency when going MCM.

You appear to be using out of date info to make these claims.

"monolithic is ALWAYS more efficient than a multi-die for the same circuit"

Monolithic means the ends of the die have much more distance between them than if allowing vertical. How in the world can you then put the disclaimer, "for the same circuit". Almost by definition, it can't be the same circuit. The power needed to move data across a large monolithic die, end to end, is a cubic+ function of distance. Sure you can then add caches, etc to minimize this, but we're back to the phrase "for the same circuit".

Finally here is TSMC's data on connection efficiency for several methods. As we notice, SoIC is 450+X as efficient as a 2.5D multi die approach. I would call that a game changer, where old models have to be retired.

With the reduced data path lengths of vertical 3D die stacking, I would make the claim that heat mitigation problems is the only limiting factor preventing widespread use.

 

[xpea]

Sure, but why is AD102 a 'mere' 600 mm2 and not 900 mm2 to match the real estate of the N31? There is a limit with monolithic designs.

I totally agree. I always said that MCM makes sense when you are limited by reticule limit and/or you want better yields.
For AD102 vs Navi31, maybe Nvidia believed that they can compete with a monolithic. Or maybe they have something else under their sleeve

 

[xpea]

The die sizes are smaller, overall, for AMD chiplets, which means you get more dies per wafer. That is the whole point of going chiplet. Its easier to get plenty of 350 mm2 dies from one wafer, than it is to get one large 700 mm2, that you have to sell then to customers.

Thats the main difference.

I did a quick check and you are wrong
AD102 die 600mm2 (24x25):


You get 82 good dies per wafer for RTX4090

Navi31 GDC die 350mm2 (18x19)


You get 156 good dies, which is 78 RX7900XT and you must add the IO die + interconnect

in this particular case, monolithic is better

 

[Glo.]

I did a quick check and you are wrong
AD102 die 600mm2 (24x25):
View attachment 59583

You get 82 good dies per wafer for RTX4090

Navi31 GDC die 350mm2 (18x19)
View attachment 59584

You get 156 good dies, which is 78 RX7900XT and you must add the IO die + interconnect

in this particular case, monolithic is better

Where do you get the info that AD102 is 600 mm2?

 

[xpea]

Where do you get the info that AD102 is 600 mm2?

I have my own source, it's all over the web + the usual twittos. Google AD102 die size

 

[Glo.]

I have my own source, it's all over the web + the usual twittos. Google AD102 die size

I wonder how Nvidia will pack 80% more SMs/ALUs on a node that provides 40% density gain, while also increasing clocks and cache sizes, by an order of magnitude.

Let me remind everyone: AD102 is going from 6 MB of L2 cache to 96 MB of L2 cache. And caches do not scale linearly with die shrinks.

If accounting for everything, we are looking at AD102 die size of 660-720 mm2. Depending on the density.

 

[xpea]

I wonder how Nvidia will pack 80% more SMs/ALUs on a node that provides 40% density gain, while also increasing clocks and cache sizes, by an order of magnitude.

Check your numbers.
Samsung 8nm is their glorified 10NM optimized for HP with a density of 52 MTr/mm2
TSMC N4 has a density above 170MTr/mm2
Of course, all these numbers are max theory
In real world, we have:
GA102 is 28.3B Tr for 628mm2 = 45Mtr/mm2
H100 is 80B Tr for 800mm2 = 88MTr/mm2

No issue to reach 600mm2 for the rumored AD102 specs and they are even some space left for surprises

Edit: Taking same density as Hopper, at rumored 600mm2 AD102 will have ~53B transistors, which is ~89% more than AD102

 

[biostud]

But this is not what the rumors say. Navi31 and Navi32 have different GDC and different IO dies. Total of 4 dies. How is it better than AD102-103-104 (3dies) to cover the same market?

Edit: Don't get me wrong, MCM is the future to increase performance beyond Moore's law. it males totally sense when you need more transistors than the reticule limit. Regarding cost savings, well the true is that Navi31 is more expensive than AD102. When we will have something like AMD CPUs, ie 4~8 CCX dies and one IO die per SKU, then it will fill the MCM purpose

The MCD could be the same silicon with two memory channels disabled for 7700.
What I find a bit strange is that they supposedly should make both an 7680 and a 5120 core GDC and only make dual GDC video cards. But what do I know?

 

[moonbogg]

I don't think AMD can charge a premium over Nvidia even if AMD is substantially faster. The problem is people just don't buy AMD GPUs. There is a mental block/mindshare issue that simply STOPS many people from buying AMD cards. They just won't do it. I still see their cards as the second choice. They are the "good enough" brand if you just need faster graphics for some computer you don't really care about and don't mind if half the programs you run don't even work right. The 6800XT looked good on paper and raw performance was good, but it's still just a lackluster AMD card.
If AMD releases a card at the same price as Nvidia but AMD was 20% faster, I'd still buy Nvidia. Why? Because the Nvidia card will work where the AMD card probably won't. Also, I still have a Gsync monitor which I won't replace, so Nvidia's Gsync brand trap actually worked in that regard. Honestly, what are the chances that an AMD card works like it should for a PC VR setup? I'd give it about a 40% chance whereas I already know the Nvidia cards work great. If all I did was play flat games and not care about Gsync, then maybe I'd consider the faster AMD card. Even then, man I just don't trust the AMD cards. Mental blocks are hard to break through. The first AMD CPU I considered buying was the 5800X and I didn't only because it was out of stock and too expensive anyway. It took all of those Ryzen releases before I finally considered their latest and best to be free enough of compromises that I'd like to have one. I did buy a couple R5 2600's for my kids because they were cheap and good enough for fortnite.

 

[Aapje]

That mental block is actually one of the reasons why I am more hyped up for the 7000 cards than the 4000.

I expect AMD to be relatively low priced, for Nvidia to lose it's DLSS edge over time (making the AMD cards age like #finewine) and for AMD to draw less power. There's a good chance that AMD cards will have more memory as well. However, the VR issues and a few other things are a worry.

I also expect Nvidia to launch before and most of the people who have been waiting to the next gen to jump on that, so AMD might have better availability despite launching later.

 

[Glo.]

There's a good chance that AMD cards will have more memory as well.

Nope .

Nvidia will have larger VRAM pools.

 

[GodisanAtheist]

Nope .

Nvidia will have larger VRAM pools.

- Will be interesting to see if AMD sticks with a 256-bit bus on their IO die or goes bigger, and what kind of RAM pool we do get. That truckload of cores have to remain fed somehow...