RISC-based chip architectures, and "oldy" architectures

[Buddha Bart]

I'm doing some research for a presentation, and was wondering if anyone had some good sites where I can see detailed breakdowns (like Ace's hardware does) of an Alpha, an HP chip, perhaps ARM, etc.

Also, does anyone know where I can find similar for things like VAX and s/390?

bart

 

[SuperTool]

Patterson and Hennesy, Computer Architecture Quantitative Approach, Third edition.

 

[bizmark]

Originally posted by: SuperTool
Patterson and Hennesy, Computer Architecture Quantitative Approach, Third edition.

hah, that's what I'm reading right now for class tomorrow morning. I was going to suggest it as well. Lots of nice charts and info. Too bad it costs $$$

 

[Sohcan]

hah, that's what I'm reading right now for class tomorrow morning. I was going to suggest it as well. Lots of nice charts and info. Too bad it costs $$$

The appendices, with surveys of various ISAs, are available for download from the publisher's website:

Online appendices for RISC, x86, VAX, and System/360 ISAs.

 

[Buddha Bart]

Woah! excellent link sohcan, thank you.

bart

 

[SuperTool]

Originally posted by: Sohcan

hah, that's what I'm reading right now for class tomorrow morning. I was going to suggest it as well. Lots of nice charts and info. Too bad it costs $$$

The appendices, with surveys of various ISAs, are available for download from the publisher's website:

Online appendices for RISC, x86, VAX, and System/360 ISAs.

Just noticed that some appendices are online.
Nice.

 

[Buddha Bart]

Can someone explain this to me:

A couple of things I've read mention "Circular Register Buffer" as a technique used by many RISC architectures to minimize context-switching. Am I correct in my understanding that the CPU only allows any given procedure to see/use 32 GPRs but in actuallity there are many more registers in the chip, and using an offset state is still within those registers rather than being written out to memory?

bart

 

[SuperTool]

Actually I think it's just a SPARC specific thing. You can have register windows for each function call, and it's not limited to 32 registers, if you read that doc, it says it can allocate from 1 to 32 8 register windows to a call, there are total of up to 128 registers. I think once you run out of those, then you have to write a window back to memory to free up space for the next call.