- May 11, 2008
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I was doing some reading on this new core from Renesas.
http://www.renesasrulz.com/communit...h-memory-can-dictate-system-level-performance
According to the website i posted, the rx core does not use a smart buffer strategy combined with a wide datapath to the flash memory. For example with the ARM7TDMI cores, the older LPC series from NXP used a 128bit wide datapath to the flash memory to access 4 32 bit instructions at once. This way, the slow access time of the flash memory could be somewhat hidden as long as contiguous memory addresses are accessed. Another solution is to copy the time critical code to local sram to reduce the amount of waitstates to the absolute minimum(1 wait state ?).
ARM7TDMI
I know my good old sam7s256 does not allow the flash memory to be accessed with 1 waitstate cycle when the system clock is above 30 Mhz. I need 2 for reading from the flash memory controller and 3 for writing to the flash memory controller while my trusty ARM7TDMI core runs at 48 MHz. I need only 1 wait state for the sram but this is a fixed number.
Cortex M3
With the Cortex M3, the memory bus seems to be optimized but the flash interface has some sort of preload mechanism to a buffer known as flash accelerator (AKA cache ?) to hide the wait states of the flash memory when the flash memory runs at a higher clock speed then the maximum clock speed for 0 (?) wait states. Thus if i understand correctly, as long as contiguous memory addresses are accessed then the flash interface from the cortex M3 chips seems to behave as if it has zero wait states.
Zero wait states i assume means just 1 waitstate similar as sram ?
The RX core from renesas
With the rx core (For example the RX600)it is claimed that the flash memory itself can be accessed within 10 nanosecond clock cycles without the use of some sort of buffer or extreme wide data path to the flash memory.
Renesas claims that the various cortex M3 chips are not really that fast at all because these chips have slow flash. Is this true ?
I am going to munch through some datasheets to compile some information.
I do know that even if this RX600 chip is that much faster and the cortex M3 chips are really that much slower, the cortex M3 chips have still the advantage of having several different manufacturers and GNU GCC support.
As such locking yourself in with the vendor is not necessary and development tools are lower in price while there is a large community support.
Does anybody have some experience when it comes to the various Cortex M3 cores and / or the RX600 core ?
I want to build experience with the new cortex M3 chips. I have been looking at a lot of different chips but i think will select the LPC1768 or LPC1769 from NXP over the LM3S1968 from Texas Instruments or the other chips from ST.
The RX600 core question : I just would like to know more about because of my work.
http://www.renesasrulz.com/communit...h-memory-can-dictate-system-level-performance
According to the website i posted, the rx core does not use a smart buffer strategy combined with a wide datapath to the flash memory. For example with the ARM7TDMI cores, the older LPC series from NXP used a 128bit wide datapath to the flash memory to access 4 32 bit instructions at once. This way, the slow access time of the flash memory could be somewhat hidden as long as contiguous memory addresses are accessed. Another solution is to copy the time critical code to local sram to reduce the amount of waitstates to the absolute minimum(1 wait state ?).
ARM7TDMI
I know my good old sam7s256 does not allow the flash memory to be accessed with 1 waitstate cycle when the system clock is above 30 Mhz. I need 2 for reading from the flash memory controller and 3 for writing to the flash memory controller while my trusty ARM7TDMI core runs at 48 MHz. I need only 1 wait state for the sram but this is a fixed number.
Cortex M3
With the Cortex M3, the memory bus seems to be optimized but the flash interface has some sort of preload mechanism to a buffer known as flash accelerator (AKA cache ?) to hide the wait states of the flash memory when the flash memory runs at a higher clock speed then the maximum clock speed for 0 (?) wait states. Thus if i understand correctly, as long as contiguous memory addresses are accessed then the flash interface from the cortex M3 chips seems to behave as if it has zero wait states.
Zero wait states i assume means just 1 waitstate similar as sram ?
The RX core from renesas
With the rx core (For example the RX600)it is claimed that the flash memory itself can be accessed within 10 nanosecond clock cycles without the use of some sort of buffer or extreme wide data path to the flash memory.
Renesas claims that the various cortex M3 chips are not really that fast at all because these chips have slow flash. Is this true ?
I am going to munch through some datasheets to compile some information.
I do know that even if this RX600 chip is that much faster and the cortex M3 chips are really that much slower, the cortex M3 chips have still the advantage of having several different manufacturers and GNU GCC support.
As such locking yourself in with the vendor is not necessary and development tools are lower in price while there is a large community support.
Does anybody have some experience when it comes to the various Cortex M3 cores and / or the RX600 core ?
I want to build experience with the new cortex M3 chips. I have been looking at a lot of different chips but i think will select the LPC1768 or LPC1769 from NXP over the LM3S1968 from Texas Instruments or the other chips from ST.
The RX600 core question : I just would like to know more about because of my work.
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