release date of Venice core for 64's?

[SylEm]

Anyone know the release date of the Venice cores for the AMD 64's? And approximately the price?

1

 

[Streckfus]

Originally posted by: SylEm
Anyone know the release date of the Venice cores for the AMD 64's? And approximately the price?

1

Release date is supposed to be April 4, 2005. No idea about the price.

 

[SylEm]

^^do you know if its suppose to be better than the Winchesters?

1

 

[Jeff7181]

Originally posted by: SylEm
^^do you know if its suppose to be better than the Winchesters?

1

Yes.

Why do you keep putting a 1 after your questions?

 

[SylEm]

^^Sorry man, I'm on hip hop forums mostly, and thats kinda like my sig in a sense. 1 = one love.....

since I run my own board its habbit, I appologize if it bothers u...

1..lol

 

[bjc112]

Dude,

Don't put 1 for One love..

Please don't put it every post either

oNe

 

[Brian23]

You're supposed to do it like this!!!!!!!!!!!!!!1!!!!!!!!!!!!!!!!1!!1

 

[Promit]

Can someone clarify what Venice actually changes?

 

[C42]

SSE3 Instructions. Higher IPC(Supposively), Supposively better mem controller, Supposively SOI or sSOI. etc. Alot of speculation. There has been a review of a 3800+ and 3500+ venice at xtremesystems though. The 3800 did amazingly well on air.

 

[Shimmishim]

i think the best improvement is in the mem controller. supposedly they are good enough to run 4 x 512 megs w/o forcing the 166 divider so that's a huge benefit for those wanting to run 2 gigs of ram.

 

[Avalon]

Originally posted by: Shimmishim
i think the best improvement is in the mem controller. supposedly they are good enough to run 4 x 512 megs w/o forcing the 166 divider so that's a huge benefit for those wanting to run 2 gigs of ram.

It would be even better if you could fill your DIMMs and still utilize a 1T command rate.
In addition to the memory controller and SSE3 (which is just a checklist feature for A64) changes, there are supposedly going to be transistor changes as well. I can't remember half of the things I've heard floating around...one of which being sSOI. Anyway, the end result is that the transistors are supposed to be able to switch 25% faster at no cost in heat or anything.

 

[C42]

Yea there was something about more copper on the REV E A64's or something, not too sure, haven't heard much about that.

 

[Wicked2010]

They are also shipping free hammers with the CPU.

These hammers can be used in conjunction with red marker.

The red marker is used to draw an X on the CPU.

Then the hammer is taken in hand and is used to aim at the red X.

SMASH!!!

 

[Avalon]

Originally posted by: Wicked2010
They are also shipping free hammers with the CPU.

These hammers can be used in conjunction with red marker.

The red marker is used to draw an X on the CPU.

Then the hammer is taken in hand and is used to aim at the red X.

SMASH!!!

Hot. I'm in for two.

 

[cyto]

According to the Athlon 64 roadmap the Venice and San Diego cores will include support for SSE3 and extra layers of copper interconnects while still retaining the same L2 cache(512KB for Venice, 1024KB for San Diego). I hope the memory controller is also improved as I am looking to upgrade my 90nm 3500+ to an FX-57 and add an extra gig of OCZ. Then when Nvidia gets better game support for SLI, I will get that 2nd BFG 6800 Ultra OC card for an awesome setup!

 

[DPOverLord]

Originally posted by: Avalon

Originally posted by: Shimmishim
i think the best improvement is in the mem controller. supposedly they are good enough to run 4 x 512 megs w/o forcing the 166 divider so that's a huge benefit for those wanting to run 2 gigs of ram.

It would be even better if you could fill your DIMMs and still utilize a 1T command rate.

Out of curiousty what is teh 1T command Rate?

 

[cyto]

This BIOS feature basically determines how long the memory controller latches on and asserts the command bus. The lower the value(3T,2T,1T), the faster the memory controller can send the commands out.

Edit:The problem is that most memory controllers/motherboards severely limit the use of 1T with low latency timings and fsb/memory speeds.