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Discussion RDNA 5 + CDNA 4 Architectures Thread

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MI400 should already be CDNA5. So maybe RDNA6 & CDNA5 = UDNA? Huynh mentioned framed it as a cloud-to-client strategy, which wold match that. CDNA5 is first and RDNA6 follows. RDNA5 could be still somewhat close to RDNA2 which might be better for next-gen consoles also.
So, going forward, we’re thinking about not just RDNA 5, RDNA 6, RDNA 7, but UDNA 6 and UDNA 7. We plan the next three generations because once we get the optimizations, I don't want to have to change the memory hierarchy, and then we lose a lot of optimizations. So, we're kind of forcing that issue about full forward and backward compatibility.
 
I posted about this feature of Mi455x before, in a wrong thread. I spotted it in one of the SamiAnalysis slides.

It is additional LPDDR5x attached to the base logic die of HBM modules. AMD is apparently is using a custom die for that.
Not news, they've been trying to force tiered GPU memory into the market since MI300A and its CXL2.0 implementation.
 
Not news, they've been trying to force tiered GPU memory into the market since MI300A and its CXL2.0 implementation.

It looks like they are making it a (so far secret) feature of Mi455.

24 LPDDR5x chips could be 768 GB of memory if they use 32 GB chips, which is in addition to 432 GB of HBM4 memory.

I am not sure how NVidia Rubin competes with this, especially in inference.
 
I posted about this feature of Mi455x before, in a wrong thread.
Now I'm confused. This thread says CDNA4 (MI355X). There's a CDNA 6 thread and then there's the RDNA5/UDNA (CDNA Next) thread which can only be for CDNA5.

IDK. Someone should prob rename the threads.
 
Now I'm confused. This thread says CDNA4 (MI355X). There's a CDNA 6 thread and then there's the RDNA5/UDNA (CDNA Next) thread which can only be for CDNA5.

IDK. Someone should prob rename the threads.

I think I got my CDNA versions confused. I thought Mi400 was CDNA4
 
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