Question Raptor Lake - Official Thread

Page 94 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

Hulk

Diamond Member
Oct 9, 1999
4,525
2,519
136
Since we already have the first Raptor Lake leak I'm thinking it should have it's own thread.
What do we know so far?
From Anandtech's Intel Process Roadmap articles from July:

Built on Intel 7 with upgraded FinFET
10-15% PPW (performance-per-watt)
Last non-tiled consumer CPU as Meteor Lake will be tiled

I'm guessing this will be a minor update to ADL with just a few microarchitecture changes to the cores. The larger change will be the new process refinement allowing 8+16 at the top of the stack.

Will it work with current z690 motherboards? If yes then that could be a major selling point for people to move to ADL rather than wait.
 
  • Like
Reactions: vstar

nicalandia

Diamond Member
Jan 10, 2019
3,331
5,282
136

From the Article:

Core Count Regression
"Sapphire Rapids introduces a much larger, faster CPU core combined with more IO and acceleration features such as AMX, which all consumes area. This results in a regression in core count for a given die size vs the previous generation. A 10nm wafer can fit 84 dies of 40-core Ice Lake, but only 68 dies of 34-core Sapphire Rapids. So, despite having fewer cores, the new generation takes 24% more wafers to fit the same number of chips. This gap widens once factoring a lower yield for larger chips."
 

jpiniero

Lifer
Oct 1, 2010
15,223
5,768
136
Where are you getting this info from? Raptor Cove if anything is a Larger(due to Larger L2, but not by much) than Golden Cove. They are both built on the same process node.

AMX and the extra AVX-512 unit take up a ton of space.


If it was actually 770 mm2 (it doesn't look that big but the Toms angle isn't that great), it'd be unsellable. They can't even get OEMs to use Icelake-W.
 

nicalandia

Diamond Member
Jan 10, 2019
3,331
5,282
136
AMX and the extra AVX-512 unit take up a ton of space.
It's not that much, 1/5th at most. But what make you believe Intel will put client based Raptor Cove cores on a Monolithic Die? On the Sapphire Rapids based Xeon W9 they are using the full fat AMX/AVX-512 Core. There is no reason to believe they will not be using the Emerald Rapids Raptor Cove on those as well.
 
  • Like
Reactions: Exist50

jpiniero

Lifer
Oct 1, 2010
15,223
5,768
136
It's not that much, 1/5th at most. But what make you believe Intel will put client based Raptor Cove cores on a Monolithic Die? On the Sapphire Rapids based Xeon W9 they are using the full fat AMX/AVX-512 Core. There is no reason to believe they will not be using the Emerald Rapids Raptor Cove on those as well.

They are calling it Raptor Lake instead of Sapphire Rapids-W.
 

Exist50

Platinum Member
Aug 18, 2016
2,452
3,102
136
I didn't say doing a 34 core Raptor Lake would be worth the engineering effort. Raptor Cove is probally like half the size of the Sapphire core so you can see why they did it.
By all indications, it's Golden Cove in the full Sapphire Rapids configuration, AVX512, AMX, and 2MB L2 included. Not that client Raptor Cove would be much smaller.

If it was actually 770 mm2 (it doesn't look that big but the Toms angle isn't that great), it'd be unsellable. They can't even get OEMs to use Icelake-W.
Unsellable? Looking at how many 32c SKUs they have for SPR, it'll probably sell more units than the bigger XCC die/package. Icelake-W sucks because the performance gains are so-so over Cascade Lake, and OEMs thought Sapphire Rapids was coming sooner than it will. SPR should be a much bigger deal for workstations.
 

Exist50

Platinum Member
Aug 18, 2016
2,452
3,102
136
For anyone hoping that the CPU is released soon...

We got a glimpse at the HEDT SPR-SP build on Compute Tiles a year ago and here we are..

View attachment 68350
Pretty much all the same bugs that affect the XCC die will also affect the MCC. But the corrolary is that when one is ready, so should the other. I doubt we'll see more than a quarter gap between them, if any gap at all.
 

nicalandia

Diamond Member
Jan 10, 2019
3,331
5,282
136
Pretty much all the same bugs that affect the XCC die will also affect the MCC. But the corrolary is that when one is ready, so should the other. I doubt we'll see more than a quarter gap between them, if any gap at all.
Any particular reason for Intel going the Monolithic rout for a low core count CPU? That thing is pushing the reticle limit and i'ts not going to beat the Top of the line Xeon W9 3495X.
 

coercitiv

Diamond Member
Jan 24, 2014
6,678
14,278
136
Pretty much all the same bugs that affect the XCC die will also affect the MCC.
I was under the impression that some of the SPR inventory was not affected by the bug(s), or was it that the clients they were shipping to did not care about the problem ?

I'll try to find the source for actual wording and quote bellow. Found it transcribed by Ian Cutress on Twitter:
We're already ramping a number of SKUs of SPR starting last Q. The particular issue, wasn't affecting those SKUs, so we did another tapeout for the volume SKUs, ramping in 2H. Feel comfortable. EMR goes into the SPR platform, product is healthy for 2023.
 

nicalandia

Diamond Member
Jan 10, 2019
3,331
5,282
136
I was under the impression that some of the SPR inventory was not affected by the bug(s), or was it that the clients they were shipping to did not care about the problem ?

I'll try to find the source for actual wording and quote bellow.
It's the second part(Buggs did not affect clients workload so they ship them anyways)
 
  • Like
Reactions: Exist50

Exist50

Platinum Member
Aug 18, 2016
2,452
3,102
136
Any particular reason for Intel going the Monolithic rout for a low core count CPU? That thing is pushing the reticle limit and i'ts not going to beat the Top of the line Xeon W9 3495X.
The XCC die/package has a lot of overhead, and there's a ton of server volume on sub-flagship products. So what makes more sense for that market - to cut down the 1600+mm2 XCC to fit, or to ship a monolithic MCC die with less than half the silicon and no advanced packaging?

That's why I've always been confused about the resistance to the idea that this product exists. It makes complete economic sense. The only thing even remotely in question was whether Intel could build it.
 

Exist50

Platinum Member
Aug 18, 2016
2,452
3,102
136
They can only extract 68 Full Dies(less are fully functional due to defect rate)
Sure, there're some inefficiencies there, but it's surely far cheaper than using the XCC. And it looks like most of these dies will be going into 32c products, so they have some spare cores for yields.
 

jpiniero

Lifer
Oct 1, 2010
15,223
5,768
136
Sure, there're some inefficiencies there, but it's surely far cheaper than using the XCC. And it looks like most of these dies will be going into 32c products, so they have some spare cores for yields.

Hah. At 0.7 defects/mm2, they would get a grand total of 2 unblemished dies per wafer. It'd be like Icelake-W - completely MIA.
 

Exist50

Platinum Member
Aug 18, 2016
2,452
3,102
136
Hah. At 0.7 defects/mm2, they would get a grand total of 2 unblemished dies per wafer. It'd be like Icelake-W - completely MIA.
And where is defect density number coming from? And even if a core or two are dead, so what? As I pointed out above, they have a comfortable 2 core buffer.

I recall you were very insistent that this very product would never exist. Maybe time to rethink some assumptions?