Question Raptor Lake - Official Thread

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Hulk

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Oct 9, 1999
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Since we already have the first Raptor Lake leak I'm thinking it should have it's own thread.
What do we know so far?
From Anandtech's Intel Process Roadmap articles from July:

Built on Intel 7 with upgraded FinFET
10-15% PPW (performance-per-watt)
Last non-tiled consumer CPU as Meteor Lake will be tiled

I'm guessing this will be a minor update to ADL with just a few microarchitecture changes to the cores. The larger change will be the new process refinement allowing 8+16 at the top of the stack.

Will it work with current z690 motherboards? If yes then that could be a major selling point for people to move to ADL rather than wait.
 
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nicalandia

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Average Performance of 5 entries Geekbench for Raptor Lake 13700K/KF CPUs


Single-Core Score: 2,055
Crypto Score: 4,656
Integer Score: 1,791
Floating Point Score: 2,195

13700K/KF





 

nicalandia

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Average Performance of entries Geekbench 3 for Raptor Lake 13600K CPU


Single-Core Score: 1,964

Crypto Score: 4,868
Integer Score: 1,710
Floating Point Score: 2,065

Intel 13600K


https://browser.geekbench.com/v5/cpu/17122807



 
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yuri69

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What decision? There is zero info about AVX support on Skymont and Darkmont. If Skymont is a big architecture upgrade over Gracemont I can see them adding AVX512 to have a parity with the big cores. Remember prior to Gracemont Intels Atom didn't even support AVX2.
There is no place for AVX512 in the current Golden + Gracemont scheme. The E-cores are not power efficient, but area efficient. Thus inflating the FPU box with an AVX512 support defeats the area efficiency.

Intle would need to change the roles of their hybrid cores. Either make the E-cores power efficient (by not clocking them so damn high) or cut the fat from the P-cores and make them more area efficient.
 

FangBLade

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Apr 13, 2022
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There is no place for AVX512 in the current Golden + Gracemont scheme. The E-cores are not power efficient, but area efficient. Thus inflating the FPU box with an AVX512 support defeats the area efficiency.

Intle would need to change the roles of their hybrid cores. Either make the E-cores power efficient (by not clocking them so damn high) or cut the fat from the P-cores and make them more area efficient.
I think when 3d stacking cores come, they won't need to use E-cores at all because with 3d stacking, area efficiency is much less concern, and that's the only reason they went to big/little design, they can't create effectively more than 8 P cores with current 2d design.
 

nicalandia

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The only reason they went to big/little design, they can't create effectively more than 8 P cores with current 2d design.
That's not correct. they can make larger than 8P core CPUs See Sapphire Rapids 16 Core per Tile(one is disabled for MC) and Monolithic SPR has been spotted with 20+ Cores
 
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FangBLade

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I'm pretty sure if Intel had MCM design ready and competitive with AMD not only in performance but profit/yield too they wouldn't go in big/little avanture, big/little is partial solution to offer more than 8 cores.
 

moinmoin

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Stacked cores wouldn't help in desktop as that's increasing the heat density further which won't work well along driving frequency even higher.
 

nicalandia

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I'm pretty sure if Intel had MCM design ready and competitive with AMD not only in performance but profit/yield too they wouldn't go in big/little avanture, big/little is partial solution to offer more than 8 cores.
That's entirely different than saying they can't make them.

Sure they can make High core count on 7nm node, the issue is not profit/yield, but more on power requirements. after 10 Cores they switch to a Mesh(Mesh of Half Rings) topology and that comes at a greater power requirement costs. Lower Speeds leads to lower performance.
 

IntelUser2000

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Oct 14, 2003
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I'm pretty sure if Intel had MCM design ready and competitive with AMD not only in performance but profit/yield too they wouldn't go in big/little avanture, big/little is partial solution to offer more than 8 cores.

Yea, so why is AMD going with the same hybrid approach in Zen 5? Just because it coincided with execution flaws in the Core division doesn't mean the hybrid concept itself is a flaw.

Do you know what is the price of a single 16C/32T 7nm die? It's not that much(less than $50)

$50 is a HUGE amount for a client CPU. Besides, at the clocks K chips require it'll use 350W without the Extreme Performance Mode.

The costs are as low as possible because the initial investment and R&D required are absolutely massive.
 

maddie

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Yea, so why is AMD going with the same hybrid approach in Zen 5? Just because it coincided with execution flaws in the Core division doesn't mean the hybrid concept itself is a flaw.



$50 is a HUGE amount for a client CPU. Besides, at the clocks K chips require it'll use 350W without the Extreme Performance Mode.

The costs are as low as possible because the initial investment and R&D required are absolutely massive.
Curious. How do you know this?
 
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IntelUser2000

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Linus' comments are very interesting but I will believe it when I see it. Because the implementation will need to be absolutely rock solid.

It took them 3 years for the Turbo implementation to work. The first basic "Turbo" came out with some extreme edition version of the Core 2 mobile chips. Simply put it was garbage and it didn't work at all. Maybe 1% of the time. Things like that are why I am extra conservative on what the computer guys claim.

I'm not sure I totally agree with him here; there are different types of throughput, but I get where he's coming from: with a high enough ratio of small to big cores, you could get into a situation where you lose performance if you use AVX 512.

You are looking for performance with these instructions right? So if the extra E cores get you there, and even better compared to AVX512 then we have no problems.

It just seems like a lot of hoops to get it enabled, especially on client. Even on Ice/Tiger we still don't have full AVX-512, because the units are 256-bit width. Yes you get the benefit of the extra extensions but FPU lane increase is the biggest and we don't get that. And they're barely getting the half-width version working.

I wonder if they should have waited extra 2 years to get AVX-512 out? And I am talking based on the original 10nm timeline. We didn't have problems with SSE2, Core 2's 128-bit boost to SSE2, AVX and AVX2. Actually it was starting with AVX2 where the clocks started dropping but it was not at all serious back then.

I feel like AVX-512 was rushed out because that's what they were using to combat GPUs and other accelerators. With projects like Falcon Shores the need will diminish.

Curious. How do you know this?

It's rumors right now and quite widespread one at that. We know Zen 4 cutdown version called Zen 4c is official. That's what being used on Bergamo. Charlie at S|A says the 128 core version is about 2x the performance of Milan, so after accounting for scaling it's at Zen 3 levels of performance per core and maybe 5% more.

So if you take Zen 3 and take it to 5nm and apply new approaches in Zen 4 for efficiency that sounds like what 4c is. Since we know Bergamo is a cloud vendor optimized version and will probably be quite a bit smaller than Zen 4, it is not at all stretch to think they'll go hybrid.

They even have a patent for it: https://hothardware.com/news/amd-patents-biglittle-core-task-transition-ryzen-8000-zen-5
 
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scineram

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I think when 3d stacking cores come, they won't need to use E-cores at all because with 3d stacking, area efficiency is much less concern, and that's the only reason they went to big/little design, they can't create effectively more than 8 P cores with current 2d design.
How many people would be happier with a 12 real core Raptor design, instead of shittle core spamming. They would even save on die area and also gain AVX-512.
If I was the kind of individual, who buys cpu and gpu not made by AMD I would consider that among the best options.
 
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FangBLade

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How many people would be happier with a 12 real core Raptor design, instead of shittle core spamming. They would even save on die area and also gain AVX-512.
If I was the kind of individual, who buys cpu and gpu not made by AMD I would consider that among the best options.
Fact, 12 P cores would be monster both in ST and MT, also because all cores are equal they don't require special optimization, and also doesn't suffer from latency like when P and E cores communicate, in the short: no regression at all. I would buy Intel no matter what price if they create 12P cores.
 

nicalandia

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How many people would be happier with a 12 real core Raptor design, instead of shittle core spamming. They would even save on die area and also gain AVX-512.
If I was the kind of individual, who buys cpu and gpu not made by AMD I would consider that among the best options.

Fact, 12 P cores would be monster both in ST and MT, also because all cores are equal they don't require special optimization, and also doesn't suffer from latency like when P and E cores communicate, in the short: no regression at all. I would buy Intel no matter what price if they create 12P cores.
What are you guys on about? 12P Core will be nearly as big as the 13900K and be Slower in MT than the 13900K and 7950X. It would effectively compete with the 7900X.

1662847668038.png
 
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HurleyBird

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You are looking for performance with these instructions right? So if the extra E cores get you there, and even better compared to AVX512 then we have no problems.

The problem is that the OS and thread director would really have no way to know that in advance. So, you might see an AVX 512 flag and use that binary, even if the tradeoff may not be worth it. You can't dynamically switch between AVX 512 with only P cores and AVX2 with all cores to see which performs better.
 

Exist50

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I think when 3d stacking cores come, they won't need to use E-cores at all because with 3d stacking, area efficiency is much less concern, and that's the only reason they went to big/little design, they can't create effectively more than 8 P cores with current 2d design.
Die stacking is a "rising tide lifts all boats" kind of situation. The same area (and thus cost) advantages exist regardless of the technology used. So long as Atom maintains a significant PPA gap vs Core, it will have reason to exist in the lineup.
 
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zir_blazer

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According to this, only SKUs from the 13600K upwards are actual brand new Raptor Lake dies, and everything below (Including 13600) is just one of the two existing Alder Lake dies. This reminds me of Coffee Lake generation where the 4C models were Kaby Lake dies on a slighty new, incompatible package just because they decided to make a new LGA 1151 socket revision.
 
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jpiniero

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According to this, only SKUs from the 13600K upwards are actual brand new Raptor Lake dies, and everything below (Including 13600) is just one of the two existing Alder Lake dies. This reminds me of Coffee Lake generation where the 4C models were Kaby Lake dies on a slighty new, incompatible package just because they decided to make a new LGA 1151 socket revision.

The i3 uses the smaller Alder Lake die actually.
 

IntelUser2000

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The problem is that the OS and thread director would really have no way to know that in advance. So, you might see an AVX 512 flag and use that binary, even if the tradeoff may not be worth it. You can't dynamically switch between AVX 512 with only P cores and AVX2 with all cores to see which performs better.

I meant back to what Linus has said at RWT forums. If your choice is between using an AVX-512 for throughput versus E cores, if the latter is better than it doesn't really matter.

If AVX-512 never comes back to client but Intel comes with a super duper hybrid CPU people will still ask "what if you could add AVX-512 on top" and likely still complain but that would be little more than a purist line of thought and not practical.
 

IntelUser2000

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The problem is that the OS and thread director would really have no way to know that in advance. So, you might see an AVX 512 flag and use that binary, even if the tradeoff may not be worth it. You can't dynamically switch between AVX 512 with only P cores and AVX2 with all cores to see which performs better.

This is what I mean in practice it's very difficult if not almost impossible. If you do as Linus suggests and switches to P-core only when it detects AVX-512 instructions, it sounds great. But how do you know if it'll be even better if you turned on E cores instead of all crunching AVX2?

You never get twice the performance for twice the vector units anyway. You only speed up the portion and that's pretty much the maximum gain you can get, even if you can accelerate it to be instant just for that portion of code.

I think the simplest is either they eventually deprecate the instruction or better yet future generations of E cores getting AVX-512 support. That's what makes Moore's Law so great. Eventually you get everything you want.
 

TESKATLIPOKA

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What are you guys on about? 12P Core will be nearly as big as the 13900K and be Slower in MT than the 13900K and 7950X. It would effectively compete with the 7900X.

View attachment 67387
True, but It also depends on how many threads you want to use.
If you use APPs with 9-13 threads, then 12 P-cores will be faster, 12 threads being the highest point providing up to ~20% performance. At 14-31 threads the 13900K will be faster and faster, until at 32 threads It will top at ~30-35%.
7950x will be comparable up to 12 threads, and after that It will win thanks to more cores.
This lower performance at lower thread count is a disadvantage why I would prefer 7950x and not 13900k even If It had a bit higher absolute 32 threads performance.
 

DrMrLordX

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Apr 27, 2000
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You are looking for performance with these instructions right? So if the extra E cores get you there, and even better compared to AVX512 then we have no problems.

It would be nice if Intel could just put extra registers on Gracemont/its successors so that they could handle expanded AVX instuctions without necessarily granting any more throughput when executing them. Not sure AVX512 works that way though. I think it would work since, for example, we have client cores like Sunny Cove and Willow Cove with AVX512 but limited 256b throughput. In any case, the registers themselves don't require that much silicon area, if I recall correctly. That way the Golden/Raptor Cove cores could increase their throughput on workloads that benefit more from instruction-level parallelism than thread-level parallelism.

What are you guys on about? 12P Core will be nearly as big as the 13900K and be Slower in MT than the 13900K and 7950X. It would effectively compete with the 7900X.

I've ranted on and on about this earlier in Alder Lake's run, but @TESKATLIPOKA pretty much nailed it on the head already. Having more Cove cores would overall benefit users since many workloads have limits to how many threads they can scale to.
 

uzzi38

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If you run emulators AVX512 could be beneficial.
This is the one place where I'm hyped for Zen 4 - for use in handhelds. I have the Steam Deck currently and the chip's low ST boost really hurts it for PS2 emulation in some cases, like Ratchet and Clank it dips below 60fps in moderately intensive scenes.

Zen 4 with the ability to hit drastically higher clocks at the same power combined with AVX-512 should make a much more competent handheld chip for emulation in general.