Question Raptor Lake - Official Thread

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Hulk

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Since we already have the first Raptor Lake leak I'm thinking it should have it's own thread.
What do we know so far?
From Anandtech's Intel Process Roadmap articles from July:

Built on Intel 7 with upgraded FinFET
10-15% PPW (performance-per-watt)
Last non-tiled consumer CPU as Meteor Lake will be tiled

I'm guessing this will be a minor update to ADL with just a few microarchitecture changes to the cores. The larger change will be the new process refinement allowing 8+16 at the top of the stack.

Will it work with current z690 motherboards? If yes then that could be a major selling point for people to move to ADL rather than wait.
 
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Kosusko

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Nov 10, 2019
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The 8+16 Raptor Lake die is big enough as it is. Plus you have to factor in time to market... Intel's just going to have to eat this one.



It's going to get added to the Atom cores at some point.

As previously announced, as the successor to Intel’s existing Knights Corner (1st generation Xeon Phi), Knights Landing makes the jump from using Intel’s enhanced Pentium 1 (P54C) x86 cores to using the company’s modern Silvermont x86 cores, which currently lie at the heart of the Intel’s Atom processors. These Silvermont cores are far more capable than the older P54C cores and should significantly improve Intel’s single threaded performance. All the while these cores are further modified to incorporate AVX units, allowing AVX-512F operations that provide the bulk Knights Landing’s computing power and are a similarly potent upgrade over Knights Corner’s more basic 512-bit SIMD units.
source:
 

Asterox

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Cinebench likes the whole 30 MiB Cache available on the 12900K, Alder Lake with Smaller total L3 Cache allowed per CPU will have lower MT Performance.

View attachment 67366

Intel i9 12900K 6C/12T with 30 MiB L3$ @5.1 Ghz: 15,970 Points

Intel i5 12400 6C/12T with 18MiB L3$ @5.1 Ghz: 14,789 Points(8% lower than 12900K at ISO Speed and ISO Cores/Threads)


The issue is compounded in this extreme case...

View attachment 67367

It's not so much that Cinebench loves Extra Cache, but that Golden Cove gets better performance the more L3 Cache you feed it. The Poor Celeron is Starved with only 4MiB of total system.

No, Cinebench do not care too much about L3 Cache size or system memory speed.

As an example take these two Zen 2 processors, because of the very big difference in L3 cache size.There are plenty of applications that do not burden/not need the large L3 cache.

R5 4650G, 8mb L3 Cache

R5 3600, 32mb L3 Cache






As you see, monolithic Renoir APU is still a faster processor in several cases.

Gaming comparison with discrete GPU, there is a big difference(not always)between the size of the L3 cache.
 

nicalandia

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No, Cinebench do not care too much about L3 Cache size or system memory speed.
No, but Golden Cove Clearly chokes when it only has 2 MiB per core as clearly seen on the Benchmark I posted(If you would like to dispute that you can take that with techspot)


As an example take these two Zen 2 processors, because of the very big difference in L3 cache size.There are plenty of applications that do not burden/not need the large L3 cache.
That just shows that AMD Built Zen with plenty of Cache.
 
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nicalandia

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They are going to have to because AMD has it.
Intel made that decision many years ago and will be sticking with it at least until 2030.

Meteor Lake, Arrow Lake, Luna Lake and Nova Lake e cores((Gracemont/Crestmont/Skymont/Darkmont) will not incorporate AVX512

This dessition was made may years ago and they just don't care that AMD has incorporated that ISA on their CPU design. It's a niche product that helps IA and other programs. AMD just incorporated because they use the same Chiplet from desktops to high end servers so it makes financial sense for them(because they have a larger pool of chiplets that they can bin)
 
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Asterox

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No, but Alder Lake Clearly chokes when it only has 2 MiB per core as clearly seen on the Benchmark I posted(If you would like to dispute that you can take that with techspot)

That just shows that AMD Built Zen with plenty of Cache.

Yes, with Zen 2/Game Cache slogan in the foreground quite logically. :grinning:

AMD 3D V-Cache on Desktop, Game Cache GTI Turbo etc.

Yes we now, Large L3 Cache it can bring great benefit in various server or HPC applications.

The more L3 Cache the better, but however it is much better to increase the significantly faster L2 cache=Zen 4.

 

Exist50

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Aug 18, 2016
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As previously announced, as the successor to Intel’s existing Knights Corner (1st generation Xeon Phi), Knights Landing makes the jump from using Intel’s enhanced Pentium 1 (P54C) x86 cores to using the company’s modern Silvermont x86 cores, which currently lie at the heart of the Intel’s Atom processors. These Silvermont cores are far more capable than the older P54C cores and should significantly improve Intel’s single threaded performance. All the while these cores are further modified to incorporate AVX units, allowing AVX-512F operations that provide the bulk Knights Landing’s computing power and are a similarly potent upgrade over Knights Corner’s more basic 512-bit SIMD units.
source:
The Forest line is for cloud, not HPC. Cloud cares far more about int performance than fp.
 

mikk

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Intel made that decision many years ago and will be sticking with it at least until 2030.

Meteor Lake, Arrow Lake, Luna Lake and Nova Lake e cores((Gracemont/Crestmont/Skymont/Darkmont) will not incorporate AVX512


What decision? There is zero info about AVX support on Skymont and Darkmont. If Skymont is a big architecture upgrade over Gracemont I can see them adding AVX512 to have a parity with the big cores. Remember prior to Gracemont Intels Atom didn't even support AVX2.
 

HurleyBird

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Apr 22, 2003
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What decision? There is zero info about AVX support on Skymont and Darkmont. If Skymont is a big architecture upgrade over Gracemont I can see them adding AVX512 to have a parity with the big cores. Remember prior to Gracemont Intels Atom didn't even support AVX2.

Or alternatively, improve thread director and work with OS schedulers so that little cores don't need AVX512. This was possibly the original intention, seeing as AL and RL big cores have physical AVX512 eating up gobs of die area.
 
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nicalandia

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What decision? There is zero info about AVX support on Skymont and Darkmont. If Skymont is a big architecture upgrade over Gracemont I can see them adding AVX512 to have a parity with the big cores. Remember prior to Gracemont Intels Atom didn't even support AVX2.
It's just Not going to happen.
 

moinmoin

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Zen 4c has it...
Like I said they will put it in Atoms. I'm sure PR hates it that AMD has AVX-512 but the client CPUs don't.
It's certainly an interesting turn of events. Intel used to add more and more instructions while AMD refrains to add its own, instead seeking to catch up after some time. Now suddenly AMD finds itself supporting one of Intel's latest instructions (ignoring AMX) across its whole upcoming product range at a time Intel itself deactivated it (client) or appears to make it pay-more-to-unlock (server).
 
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nicalandia

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It's just your hope it won't happen, you have to make it clear.
It's a business decision that Intel has made that will be implemented through Software Defined Silicon(SDSi). First implementation will be on Sapphire Rapids-SP, SPR-X.

How many Vendors or Individuals are willing to pay for a Feature they don't need/know about on Laptops and Desktops? They just fuse the AVX-512 FPU Units and call it a day.
 

IntelUser2000

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Oct 14, 2003
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They could have done it like in Tiger Lake, one AVX512 FPU Register. But then they would have have to redesign the Golden/Raptor Cove/Redwood Cove for each segment(Server and Client), but it's cheaper to design one single core and just segment it.

It still takes up quite a bit of space even not adding 512-bit vector unit like they do on server. You still need the extra space for registers and stuff you know? Sunny/Willow Cove having large FPU block for AVX-512 is despite the fact it physically doesn't have 512-bit units and is same as Skylake client having 2x-256.

The fact that it's not added uniformly across the product line suggests 512-bit vector is the point where it's getting a bit too large in terms of power use and area.

Intel made that decision many years ago and will be sticking with it at least until 2030.

Oh almighty nicalandia, have mercy on us! Perhaps in your infinite graciousness can tell us what's in store for the world in 10 years?
 
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IntelUser2000

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i wouldn't say that at all, scalar over SIMD sure but then things like TLS throughput still matter alot.

Gracemont is AVX2 but with 128-bit vector units rather than 256-bit like Sandy Bridge and onwards. Being AVX2 it supports FMA but it would take 2 cycles.

Or alternatively, improve thread director and work with OS schedulers so that little cores don't need AVX512. This was possibly the original intention, seeing as AL and RL big cores have physical AVX512 eating up gobs of die area.

It will be quite difficult I imagine. It's like making Hyperthreading have no losses in single threaded workloads. You can minimize it and they have done a damn good job since Nehalem but it's not 100%.

It's worse here because you have the potential of causing application crash. You can change some newer ones to support it but older ones won't and Intel will get a lot of flack for it. That's what happens on a general purpose chip like a CPU.

Or that they won't fix the scheduler problem, or that they won't have a AVX-512 chiplet?

When you say "scheduler problem" you mean regarding two cores in a chip with different ISA's?

Again that's a very, very difficult if not almost impossible problem. Because when the application expects AVX-512 but some cores don't have it, it'll crash. Yes you can update the newer ones but you'll inevitably run into ones that don't. And you know automated approaches can't do 100% and require manual intervention for lots of scenarios.

The easiest way is down the line E cores eventually have AVX-512. I wouldn't be surprised if they reduce the ST gap between E and P cores to 15-20%. When the cores get that powerful maybe they'll get an upgrade to 256-bit units and they can add AVX-512.
 
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LightningZ71

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I can see a scenario where, on the next big node/density jump, they add a half throughput avx-512 unit to the mont cores. The density increase allows them to afford to add it to the monts and keep the 4 to 1 size ratio with the coves that will grow even larger as they continue to fight for parallelism and a larger out if order window.
 

HurleyBird

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Sometime back there was a good discussion in RealWorldTech about this subject RealWorldTech

Linus is saying exactly what my intuition assumed would be the case, that there isn't a fundamental problem, and at a high level it actually looks simple, but it's still novel and will take time to get right.

Besides that, Linus takes umbrage with Intel's approach to big.LITTLE because the "throughput cores" lack the "throughput vector extension" while the "non-throughput cores" have the "throughput vector extension." I'm not sure I totally agree with him here; there are different types of throughput, but I get where he's coming from: with a high enough ratio of small to big cores, you could get into a situation where you lose performance if you use AVX 512.
 

moinmoin

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Again that's a very, very difficult if not almost impossible problem. Because when the application expects AVX-512 but some cores don't have it, it'll crash.
AMD has a patent where such unsupported instructions would be caught and the process transparently moved to a core supporting it. This would move some of the scheduling complexity into the hardware which has a better picture of its own resources. But I'm not sure how feasible such a mixed approach is in today's OS ecosystem where all software schedulers expect to have complete control.
 

nicalandia

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Average Performance of 25 entries Geekbench 5 for Raptor Lake 13900/K/KF CPUs


Single-Core Score: 2,208

Crypto Score: 5,312

Integer Score: 1,915

Floating Point Score: 2,324


Intel Core i9-13900K




















Intel Core i9-13900KF






Intel Core i9-13900



 
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