Question Raptor Lake - Official Thread

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dullard

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May 21, 2001
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I'm not going to waste time arguing a point that is frankly obvious with you, when you clearly didn't read my earlier post.

You're spouting off a bunch of things you can plug in. That's great, but those things are all constrained by the link to the chipset.
1) If you read my bolded red text above, you'll see that I addressed exactly what you were speaking of. Intel has quadrupled that link recently. That problem is being addressed. Also, more and more is going direct to the CPU which offloads problems on that link.

2) How can you speak of chipset link constraints without discussing the number of items simultaneously communicating over that link? Define that (which is a simple task for each user) and then we can discuss if the link is a problem for that user. But without any specification of the simultaneously communicating items, we have nothing to talk about.
1660083965770.png
 
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Schmide

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Mar 7, 2002
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Looking forward intel pcie5 can only be configured 2 ways, 16x and 8x 8x. If motherboard makers want a pcie5 drive, they have to run 8x 8x. This limits the GPU to 8x, which generally means nothing; except, it seems nVidia isn't going to do pcie5 in their next flagship. If you're building high end nVidia/intel; your choice is, limit your GPU to 8x pcie4 and get pcie5 drive speeds, or full speed GPU at 16x pcie4 with pcie4 drive speeds.

Is 8x pcie4 enough for the next flagship GPU? Something to think about when you see pcie5 drive speed advertised on an intel motherboard.
 
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shady28

Platinum Member
Apr 11, 2004
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1) If you read my bolded red text above, you'll see that I addressed exactly what you were speaking of. Intel has quadrupled that link recently. That problem is being addressed. Also, more and more is going direct to the CPU which offloads problems on that link.

2) How can you speak of chipset link constraints without discussing the number of items simultaneously communicating over that link? Define that (which is a simple task for each user) and then we can discuss if the link is a problem for that user. But without any specification of the simultaneously communicating items, we have nothing to talk about.
View attachment 65622

Yeah I think I already explained some of that in this post.

The Z490 I have is miserable in this regard due to the DMI 3.0 x4 lanes to the chipset. A DMI 3.0 lane is basically like a PCIe 3.0 lane, bandwidth is ever so slightly faster on DMI but call it the same. Everything off the chipset, comes down to that interface.

Z590 was far better, with DMI 4.0 x4 (twice the bandwidth) and Z690 expanded to DMI 4.0 x8. From that perspective Z590 had basically the same bandwidth capability to the chipset as AMDs X570, which uses PCIe 4 x4 to its chipset, while the Z690 has significantly greater bandwidth (twice as much) by using twice as many lanes.
 

LightningZ71

Golden Member
Mar 10, 2017
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My initial point is that the HEDT market has been targeted as having 56-64 PCIe lanes available forcadd in cards for the last four+ years. The desktop market has had 4 lanes to a chipset (recently up to 8), one local x4 link for storage and an x16 that may or may not bifurcate.

That's a big gap. It hurts storage I/O for power users. Yes, its hardly relevant for most users, but that's whyvthe HEDT market was tiny, but present.

My point is that the majority of that HEDT market could be served by any of the top end desktop processors, so long as they had a way to provide the mountain of I/O that that market needs. This could be served by an HEDT chipset and high lane count motherboard without having a huge, expensive processor. Intel did a little of this with their C series chipsets for low end xeons, though they were not much of an improvement.

Just an example, the 5950x could have rwo lical x4 4.0 M.2 drives attached to the processor with an x16 4.0 link to an HEDT chipset that could provide 64 lanes of PCIe 3.0 or 4.0 connectivity that would multiplex down as needed through a root complex switch on the chipset. Yes, it would be 4x over subscribed if 4 x16 cards were attached, but it woukd still be FAR ahead of any normal desktop for HEDT purposes.

Develolment on that would be much less than a dedicated HEDT processor coupled with a dedicated socket and platform.
 
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shady28

Platinum Member
Apr 11, 2004
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My initial point is that the HEDT market has been targeted as having 56-64 PCIe lanes available forcadd in cards for the last four+ years. The desktop market has had 4 lanes to a chipset (recently up to 8), one local x4 link for storage and an x16 that may or may not bifurcate.

That's a big gap. It hurts storage I/O for power users. Yes, its hardly relevant for most users, but that's whyvthe HEDT market was tiny, but present.

My point is that the majority of that HEDT market could be served by any of the top end desktop processors, so long as they had a way to provide the mountain of I/O that that market needs. This could be served by an HEDT chipset and high lane count motherboard without having a huge, expensive processor. Intel did a little of this with their C series chipsets for low end xeons, though they were not much of an improvement.

Just an example, the 5950x could have rwo lical x4 4.0 M.2 drives attached to the processor with an x16 4.0 link to an HEDT chipset that could provide 64 lanes of PCIe 3.0 or 4.0 connectivity that would multiplex down as needed through a root complex switch on the chipset. Yes, it would be 4x over subscribed if 4 x16 cards were attached, but it woukd still be FAR ahead of any normal desktop for HEDT purposes.

Develolment on that would be much less than a dedicated HEDT processor coupled with a dedicated socket and platform.
I believe that with Alder Lake, the Z690 exceeds the total IO capabilities of the X299 2066 socket chips, i.e. the HEDT system from 2017. Those had 44 PCIe 3.0 lanes to CPU, and x4 DMI 3.0 lanes to the chipset.

You could certainly add more 'slots' to X299, but as far as total possible IO bandwidth, it should be higher on Z690. Just the 16 PCIe 5 lanes alone, has about the same bandwidth as 64 PCIe 3.0 lanes, and you can run it in two PCI 5 x8 slots to make use of RAID cards.


The newest HEDT chips are Ice Lake-W. Those have 64 PCIe 4.0 lanes off the CPU, Xeon W-3300.

Unfortunately most of the major OEMs like Dell and HP are still trying to unload their older Cascade Lake chips, like in the HP Z line and Dell Precision workstations.

These will set you back 5-10 grand or more depending on config, but they are basically the current HEDT chips.

Like this :



1660106723865.png


You can also build one yourself :

1660107802646.png
 
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moinmoin

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Just the 16 PCIe 5 lanes alone, has about the same bandwidth as 64 PCIe 3.0 lanes, and you can run it in two PCI 5 x8 slots to make use of RAID cards.
Yeah, I personally don't think bandwidth is the issue these days with PCIe 5. I don't think we'd talk about it that much if there were be an easier cheaper way to up the lane count by doubling it on lower PCIe versions and board manufacturers were to offer that option. The lane count staying the same even when going to PCIe 4 or even PCIe 3 and effectively halving the bandwidth used each step without being able to use the rest for more lanes is such a waste.
 

LightningZ71

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I'm with you for the above. Ice Lake W is a decent product and the lane count certainly is something useful. Looking specifically at the Intel platform, as compared to the W-3322 and 3335 (12 and 16 cores respectively), the 12900K and the 13700K and 13900K should run rings around them for processor throughput, both in ST and MT scenarios, save for a few cases where absolute peak memory bandwidth is absolutely essential. The 3322 is a ~$1000 processor and the 3335 is $1300. Alder and Raptor don't come close to that cost. Alder and Raptor both also have enough PCIe bandwidth coming from the processor (16 X PCIe5 lanes) to keep 4 X 16 lane PCIe 3 slots fully saturated if connected to a decent switch. There are currently precious few PCIe 4.0 (save for video cards and M.2 4X AICs) and essentially no 5.0 cards out there on the market right now, and the ones that are there aren't even capable of keeping the total bandwidth of the slots in constant use under any scenario that is representative of a real world use case. You have to get to the 24 core, $2500 3345 before you get a comparable amount of L3 cache and still loose in every case on St throughput and are going to be hard pressed to beat the 12900K, 13700K+ in MT tasks. There's no clear advantage until the 3365+ and that's well past $3000.

The situation on the AMD side is even worse with the elimination of the non-WX threadrippers. Your CPU costs are stratospheric, and the motherboards are too. There's no reason that a 7950X couldn't drive a multiplexer/switch for 4 X16 or 6-8 x8 slots and keep them all quite happy in normal use. The total RAM bandwidth from dual (quad) channel DDR5-6000 will be roughly equivalent to the quad channel Threadrippers from the 3000 series. With people paying well north of $500 for high end X570 boards and likely x670 boards, there's room in the market for an HEDT board and chipset for the 7900/7950X.

Please keep in mind, I'm proposing that the x16 link from the CPU be used for driving the PCIe slots and the chipset I/O. Since it's an HEDT platform, I'm reserving the chipset x4 PCIe link for a second processor direct M.2 slot so that there are two. If AM5 reserves an additional x4 link from the processor like we've been seeing, then a second I/O chipset can be driven from that, simplifying the first one.
 
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maddie

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Jul 18, 2010
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I'm with you for the above. Ice Lake W is a decent product and the lane count certainly is something useful. Looking specifically at the Intel platform, as compared to the W-3322 and 3335 (12 and 16 cores respectively), the 12900K and the 13700K and 13900K should run rings around them for processor throughput, both in ST and MT scenarios, save for a few cases where absolute peak memory bandwidth is absolutely essential. The 3322 is a ~$1000 processor and the 3335 is $1300. Alder and Raptor don't come close to that cost. Alder and Raptor both also have enough PCIe bandwidth coming from the processor (16 X PCIe5 lanes) to keep 4 X 16 lane PCIe 3 slots fully saturated if connected to a decent switch. There are currently precious few PCIe 4.0 (save for video cards and M.2 4X AICs) and essentially no 5.0 cards out there on the market right now, and the ones that are there aren't even capable of keeping the total bandwidth of the slots in constant use under any scenario that is representative of a real world use case. You have to get to the 24 core, $2500 3345 before you get a comparable amount of L3 cache and still loose in every case on St throughput and are going to be hard pressed to beat the 12900K, 13700K+ in MT tasks. There's no clear advantage until the 3365+ and that's well past $3000.

The situation on the AMD side is even worse with the elimination of the non-WX threadrippers. Your CPU costs are stratospheric, and the motherboards are too. There's no reason that a 7950X couldn't drive a multiplexer/switch for 4 X16 or 6-8 x8 slots and keep them all quite happy in normal use. The total RAM bandwidth from dual (quad) channel DDR5-6000 will be roughly equivalent to the quad channel Threadrippers from the 3000 series. With people paying well north of $500 for high end X570 boards and likely x670 boards, there's room in the market for an HEDT board and chipset for the 7900/7950X.

Please keep in mind, I'm proposing that the x16 link from the CPU be used for driving the PCIe slots and the chipset I/O. Since it's an HEDT platform, I'm reserving the chipset x4 PCIe link for a second processor direct M.2 slot so that there are two. If AM5 reserves an additional x4 link from the processor like we've been seeing, then a second I/O chipset can be driven from that, simplifying the first one.
Isn't this a scenario that capitalism is supposed to correct? Surely some at the motherboard manufacturers would think about a "HEDT-lite" motherboard splitting PCIe 5.0 lanes. Might AMD & Intel be "blocking" this?
 

shady28

Platinum Member
Apr 11, 2004
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So, ultimately, you refuse to accept that there have been significant but insufficient increases in the link bandwidth problem you speak of. Because that is my point that you keep arguing against.
No I just refuse to keep arguing with you about points I already made. Good thing they have an ignore button here.
 

moinmoin

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Jun 1, 2017
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Isn't this a scenario that capitalism is supposed to correct?
No? I mean if you see money in correcting it you are free to give it a try. If nobody including you sees enough money in it to start actively correcting it (instead just passively wanting it) it won't happen. That's capitalism.
 
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LightningZ71

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Well, the original point was that Raptor lake desktop, with 8 P cores and 16 E cores at its disposal would make a decent HEDT processor in it's own right. The platform that it's on seems to be the limiting factor and that there is a non-insurmountable pathway to remedy that. But, this is more a platform discussion and not a processor discussion in and of itself.
 

nicalandia

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Well, the original point was that Raptor lake desktop, with 8 P cores and 16 E cores at its disposal would make a decent HEDT processor in it's own right.
With the High Clocked and enhanced Raptor Cove cores the 13900K is rendering all but the highest core count irrelevant. 24-32 Core Sapphire Rapids-X with low base clock or Tunned 13900K Raptor Lake.
 

Exist50

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Aug 18, 2016
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With the High Clocked and enhanced Raptor Cove cores the 13900K is rendering all but the highest core count irrelevant. 24-32 Core Sapphire Rapids-X with low base clock or Tunned 13900K Raptor Lake.
Lmao, 24+ core SPR would easily beat Raptor Lake in parallel tasks. Might be some overlap in the way low end, but that would be nothing new.
 

Carfax83

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Intel Core i9-13900K Raptor Lake CPU Up To 24% Faster Than 12900K, 43% Faster Than 5950X & 68% Faster Than 5800X3D In AOTS Benchmark

This is apparently at 4K as well. This benchmark is highly multithreaded and makes excellent use of the efficiency cores.

Can't wait to see how Zen 4 stacks up against Raptor Lake in this scenario. The suspense is literally killing me! :D

I will base my new platform on either Raptor Lake or Zen 4 and gaming performance will be extremely important to me as I will be using my rig predominantly for that.
 

nicalandia

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Lmao, 24+ core SPR would easily beat Raptor Lake in parallel tasks. Might be some overlap in the way low end, but that would be nothing new.
What apps do you have in mind? Cinebench, POV and Geekbench I expect a 13900K Raptor Lake to own a 24C/48T Sapphire Rapids
 

Exist50

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What apps do you have in mind? Cinebench, POV and Geekbench I expect a 13900K Raptor Lake to own a 24C/48T Sapphire Rapids
What sufficiently parallel apps shouldn't SPR win? 8+16 is equivalent to what? Roughly 16+0 in throughput? So that's effectively a 50% core advantage for SPR plus AVX512 & AMX support plus 4x the memory channels. Raptor Lake would have to close that entire gap with pretty much just core and fabric clock speed. Iso-power, I don't see that being a winning bet.
 
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shady28

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Well, the original point was that Raptor lake desktop, with 8 P cores and 16 E cores at its disposal would make a decent HEDT processor in it's own right. The platform that it's on seems to be the limiting factor and that there is a non-insurmountable pathway to remedy that. But, this is more a platform discussion and not a processor discussion in and of itself.

You really can't and shouldn't separate platform from CPU. It would be like comparing two cars, and only being allowed to talk about their engines. It's absurd.
 

LightningZ71

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You really can't and shouldn't separate platform from CPU. It would be like comparing two cars, and only being allowed to talk about their engines. It's absurd.
Why not? The Platform CAN be flexible. PLX switches for PCIe busses have been in existence for over a decade. The very configuration of the various chipsets for both Intel and AMD processors are arbitrary decisions made in board rooms. There is no technical reason that a UEFI/chipset combination can not be released that allows Raptor Lake or AM5 to behave like a low-mid end HEDT machine. Just like cars and engines, the Chevy Small block has been through many generations and been used in many different vehicle platforms. It existed in various states of tune in Sedans, in modest coupes like the Camaro, and in high end sports cars like the Corvette in its various performance levels. The same smallblock in the Holden Comodore (AKA Pontiac G8/Chevrolet SS in the US market) gave a car with substantially different performance than a top end Corvette ZR1 of the same generation. Yes, both were/are sports cars, but, you're going to lap the Nurbegring a whole lot faster in the vette.

It's absurd to believe that the processor MUST be tied to only one platform, ever, especially when the platforms themselves are drastically different from the bottom end all the way to the top end. Look at Comet lake, the H410 to the W480 differed in DIMM count, total supported RAM (granting that's more of a bios limitation, but its still a difference), SATA ports, PCIe lanes provided, USB ports (speed and number), available display ports, integrated wireless support, Optane support, Audio feature support, VPRO support and even lithography technique. If I judged Comet lake as a product based on the H410 chipset, it would look like a MASSIVE regression from the previous generation though it provably wasn't. The only thing that a MODERN x86 processor from one of the two leading vendors is married to is the number of PCIe lanes it provides and the integrated SoC features. Both vendors provide many of their processor architectures on multiple different sockets, with AMD providing their APUs in desktop form and Mobile form and Intel doing similar for AlderLake.
 
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