Question Raptor Lake - Official Thread

[Hulk]

Since we already have the first Raptor Lake leak I'm thinking it should have it's own thread.
What do we know so far?
From Anandtech's Intel Process Roadmap articles from July:

Built on Intel 7 with upgraded FinFET
10-15% PPW (performance-per-watt)
Last non-tiled consumer CPU as Meteor Lake will be tiled

I'm guessing this will be a minor update to ADL with just a few microarchitecture changes to the cores. The larger change will be the new process refinement allowing 8+16 at the top of the stack.

Will it work with current z690 motherboards? If yes then that could be a major selling point for people to move to ADL rather than wait.

 

[moinmoin]

Talking about IPC is funny because 5800x-3d have lower performance in cinebench than regular version, while much higer performance in gaming, in couple of games like MSFS significantly better even than Intel best model.

Not really funny if you understood the following passage:

So, with the definitions settled, it should now be clear that memory hierarchy, cache design and size — as well all other architectural features of a CPU that has a bearing on the total number of cycles it takes the particular program to run — all influence the effective IPC. It should also be clear that IPC is workload dependent.

Essentially bigger cache can and should reduce the cycles a more complex workload needs waiting for data. Waiting for data most of the time is the most time consuming part of processing so there is always something in memory hierarchy, cache design and size that can be optimized further.

Going back on topic, this is exactly what surprises me about RPL increasing cache vs ADL but benchmarks so far not showing typical IPC improvements that usually follow such cache increases.

 

[Markfw]

Silly question maybe. So when is Raptor lake going to be released ? The latest I know of for Zen 4 is something on Aug 29th, and everything else on Sept 15th or so. But no word on raptor lake ? Or did I just miss it.

 

[Exist50]

Silly question maybe. So when is Raptor lake going to be released ? The latest I know of for Zen 4 is something on Aug 29th, and everything else on Sept 15th or so. But no word on raptor lake ? Or did I just miss it.

Probably will be announced at their "Innovation" event Sept 27th, with retail availability a few weeks later. That would be the typical pattern.

 

[Markfw]

Probably will be announced at their "Innovation" event Sept 27th, with retail availability a few weeks later. That would be the typical pattern.

So Zen 4 will most likely beat it to reviews, but within a month we can have a real comparison. Cool.

 

[scannall]

Probably will be announced at their "Innovation" event Sept 27th, with retail availability a few weeks later. That would be the typical pattern.

So far all I have seen in this thread and the AMD thread is people screaming at each other over which hypothetical, unavailable CPU is better. Both will be better than the previous generation, and that is all I am certain of. But please people, understand what 'leaks' and 'engineering samples' are for. Entertainment value. That's it.

In due time when they are in the wild we will have actual benchmarks of actual shipping products. My 'intuition' as it were is that Zen 4 will be a bit better. But my intuition means almost nothing. If yours is that Intel will pull ahead then great. It's yours. Own it. But until then please be kind to each other. It's not that hard, and we can all appreciate the tech advancements we all love regardless of who is ahead for the moment.

 

[Carfax83]

Going back on topic, this is exactly what surprises me about RPL increasing cache vs ADL but benchmarks so far not showing typical IPC improvements that usually follow such cache increases.

That's because most of the benchmarks we've seen so far are cache insensitive, ie cinebench, Geekbench etc...

The gaming benchmarks that Chinese leaker released on his engineering sample definitely registered an impact from the cache increase if you ask me.

 

[LightningZ71]

Given the above definition of IPC and our current personal computer design philosophy, it stands to reason that the faster a cpu core clocks relative to the ability of a memory subsystem to feed it data and instructions, the more total cycles it will waste waiting for data. So, with a constant memory subsystem, including caches, just adding click speed to the core will just enable quicker race to idle and only provide limited additional throughput. To combat this, you increase the memory subsystem throughput by using faster memory modules, expanding the L3 and L2 cache and the supporting data structures while fighting not to increase clock cycle latency for each memory request.

 

[pakotlar]

So Zen 4 will most likely beat it to reviews, but within a month we can have a real comparison. Cool.

Yep super exciting. Been years since weve had 2 competitive CPUs launch near each other. Feels like were back in Coppermine vs Athlon days.

 

[nicalandia]

I wouldnt call that a stomping. 2k faster for 2.5x the cores, and half the single threaded performance, and more power.

At least its better to what a Release(Or close to it E3 QS sample) Sapphire Rapids has shown so far.

Raptor Lake 13900K is so far shown pretty good MT numbers, perhaps too good to overshadow Sapphire Rapids-X HEDT Parts? Due to low clocks and lack of e cores even the 32 Core SKUs should fall behind Raptor Lake 13900K

Unknown - Geekbench

Benchmark results for an Unknown with an Intel Xeon Platinum 8480+ processor.

browser.geekbench.com

 

[LightningZ71]

Both Intel and AMD are doing the HEDT market a disservice by not providing a high I/O chipset for their desktop parts. With 8 lanes of PCIe 4-5 coming from the latest chips into a root hub, or by repurposing the 16 lanes of PCIe 5 that are going to the first x16 slot, there could be a lot of lanes made available on motherboards with a more complex chipset and an additional few layers. While they would certainly be more expensive to make, it wouldn't be anywhere near the price of the lightly tweaked server chips that they are selling in the workstation market. Both the 7950x and the 13900k are well into the midrange of previous gen HEDT chips with respect to MT performance and they have markedly better ST performance to boot.

 

[dullard]

Both Intel and AMD are doing the HEDT market a disservice by not providing a high I/O chipset for their desktop parts. With 8 lanes of PCIe 4-5 coming from the latest chips into a root hub, or by repurposing the 16 lanes of PCIe 5 that are going to the first x16 slot, there could be a lot of lanes made available on motherboards with a more complex chipset and an additional few layers. While they would certainly be more expensive to make, it wouldn't be anywhere near the price of the lightly tweaked server chips that they are selling in the workstation market. Both the 7950x and the 13900k are well into the midrange of previous gen HEDT chips with respect to MT performance and they have markedly better ST performance to boot.

How many do you need? Both Alder Lake and Raptor Lake add more PCIe lanes. Not dozens more, but more.

 

[shady28]

How many do you need? Both Alder Lake and Raptor Lake add more PCIe lanes. Not dozens more, but more.

He's talking about the connection from the CPU to the chipset.

That's a very relevant thing to both platforms. Intel has a DMI 4 x8 link (same as PCIe 4 x8 in bandwidth) to its Z690 chipset. Current Zen 3 X570 has a PCIe 4 x4 link to the chipset.

This, frankly, is broken. If you have IO occurring on multiple devices at once, you will see speed degradation. Since you always have some IO occuring on multiple devices even when benching an individual component (i.e. your NIC / Wifi is still active, you still have mouse/kb, might have bluetooth running etc) there is a performance hit.

This is actually more important than all the devices you can plug into the chipset at this point, because the current chipsets already take a hit when using a fast PCIe 4 x4 m.2

That shows up in proper motherboard benchmarks too (2nd image) when they measure disk IO as part of the review (a big miss that many reviewers do not do this). Keep in mind, the disk IO benchmark shown on a pcie 4 x4 m.2 is *only testing one device at a time*.

The real impact is felt when, for example, backing up that PCIe 4 x4 m.2 to a USB 2 Gen 2 or 2x2 drive. The bandwidth is all shared, performance drops off a cliff. This is a common use case.

 

[dullard]

He's talking about the connection from the CPU to the chipset.

That's a very relevant thing to both platforms. Intel has a DMI 4 x8 link (same as PCIe 4 x8 in bandwidth) to its Z690 chipset. Current Zen 3 X570 has a PCIe 4 x4 link to the chipset.

Pretending that he was talking about the DMI link, even that has recently been upgraded from DMI 3.0 to DMI 4.0 (double the bandwidth) on Alder Lake. That double bandwidth helps a lot with bottlenecks. Also the direct from CPU lanes have been upgraded from PCI 4.0 to PCI 5.0 (again double the bandwidth). Even the DDI lanes have increased, so you can run your M.2 drive to USB example without going through the chipset at all.

Which goes back to the question that I asked: how many lanes does he need? Or in terms of bandwidth, how much bandwidth is needed?

 

[shady28]

Pretending that he was talking about the DMI link, even that has recently been upgraded from DMI 3.0 to DMI 4.0 (double the bandwidth) on Alder Lake. That double bandwidth helps a lot with bottlenecks.

Yes I know that, I pointed out in my post that it was DMI 4 x8 on Z690, on an earlier post on this topic. Intel does have a better link (twice the bandwidth) to the chipset on Z690 than Zen 3 X570 chipsets. I'm hoping they increase this to DMI 5.0 so the link is capable of supporting a pair of full speed PCIe 5 x4 drives from the chipset. AMD if they increase their link to PCIe 5 x4 on X670 boards, will be up to Intel Z690 speeds.

By the way when he says this, you can bet it is about the chipset :

With 8 lanes of PCIe 4-5 coming from the latest chips into a root hub, or by repurposing the 16 lanes of PCIe 5 that are going to the first x16 slot, there could be a lot of lanes made available on motherboards with a more complex chipset and an additional few layers.

Also the direct from CPU lanes have been upgraded from PCI 4.0 to PCI 5.0 (again double the bandwidth).

Source? I haven't found anything on either platform about this.

Even the DDI lanes have increased, so you can run your M.2 drive to USB example without going through the chipset at all.

Again, source on DMI / PCIe lanes on the new chipsets?

You can run *one* m.2 drive without going through the chipset. Again, on this topic I stated earlier that if all you have is an x16 GPU and one m.2 you are fine on any of these platforms.

You won't even use the chipset for anything but USB / ethernet. If that's you, you don't even need an X6XX or Z6XX chipset.

For those of us who like to do something ultra rare, like backup our drives with all our personal financial information and work, to an external USB 3.2 gen 2 SSD or SATA drive, and already have two or more m.2 drives, this matters.

 

[dullard]

Source? I haven't found anything on either platform about this.
...
Again, source on DMI / PCIe lanes on the new chipsets?

I'm not sure why you need sources for additional IO on Alder Lake as it has been public knowledge for quite some time. But here goes.

• Rocket Lake: https://extremehw.net/all-reviews/11900k-z590-overclocking-guide/
• Alder Lake: https://i.pcmag.com/imagery/articles/00pFcBd5Oh7XFo7rV30jPxY-7.fit_lim.size_768x.jpg
• Raptor Lake: https://cdn.videocardz.com/1/2022/07/Intel-Raptor-Lake-S-PCH.jpg

For IO, Rocket Lake:

• Went from x4 DMI 3.0 to x8 DMI 3.0 on the connection from the CPU to the chipset.
• Added 3 USB 3.2 2x2 ports on the chipset.
• Added 4 USB 3.2 2x1 ports on the chipset.

For IO, Alder Lake:

• Switched from 1x16 PCIe 4.0 to 1x16 PCIe 5.0 directly from the CPU.
• Went from 3 DDI ports to 4 DDI ports directly from the CPU. Just put in a cheap DDI to USB converter and you can run an additional USB drive direct from the CPU and doesn't impact the bandwidth going between the CPU and the chipset.
• Went from x8 DMI 3.0 to x8 DMI 4.0 on the connection from the CPU to the chipset. So, in two generations this connection speed quadrupled.
• Went from 24 PCIe 3.0 ports to 28 PCIe ports (12 PCIe 4.0 and 16 PCIe 3.0) on the chipset.
• Went from 6 SATA 6 Gb/s ports to 8 SATA 6 Gb/s ports on the chipset.
• Went from 3 USB 3.2 2x2 ports to 4 USB 3.2 2x2 ports on the chipset.

For IO, Raptor Lake:

• Adds additional PCIe 4.0 ports on the chipset (quantity added not yet revealed).
• Adds additional USB 2x2, PCIe 3.0, and SATA 3.0 ports on the chipset (quantity added not yet revealed).
• Is now fully Thunderbolt 4.0 compliant.

I could go into really minor details like the sound no longer being on the PCIe lanes at all. But one extra lane here or there probably doesn't matter much.

So, I take offense with phrases such as "not providing a high I/O" when detail is not provided to list how much IO they want. IO has been increased substantially in recent iterations. It just hasn't been enhanced enough for some users. So my question, how much is really needed?

 

[pakotlar]

I'm not sure why you need sources for additional IO on Alder Lake as it has been public knowledge for quite some time. But here goes.

• Rocket Lake: https://extremehw.net/all-reviews/11900k-z590-overclocking-guide/
• Alder Lake: https://i.pcmag.com/imagery/articles/00pFcBd5Oh7XFo7rV30jPxY-7.fit_lim.size_768x.jpg
• Raptor Lake: https://cdn.videocardz.com/1/2022/07/Intel-Raptor-Lake-S-PCH.jpg

For IO, Alder Lake:

• Switched from 1x16 PCIe 4.0 to 1x16 PCIe 5.0 directly from the CPU.
• Went from 3 DDI ports to 4 DDI ports directly from the CPU. Just put in a cheap DDI to USB converter and you can run an additional USB drive direct from the CPU and doesn't impact the bandwidth going between the CPU and the chipset.
• Went from x8 DMI 3.0 to x8 DMI 4.0 on the connection from the CPU to the chipset.
• Went from 24 PCIe 3.0 ports to 28 PCIe ports (12 PCIe 4.0 and 16 PCIe 3.0) on the chipset.
• Went from 6 SATA 6 Gb/s ports to 8 SATA 6 Gb/s ports on the chipset.
• Went from 3 USB 3.2 2x2 ports to 4 USB 3.2 2x2 ports on the chipset.

For IO, Raptor Lake:

• Adds additional PCIe 4.0 ports on the chipset (quantity added not yet revealed).
• Adds additional USB 2x2, PCIe 3.0, and SATA 3.0 ports on the chipset (quantity added not yet revealed).
• Is now fully Thunderbolt 4.0 compliant.

I could go into really minor details like the sound no longer being on the PCIe lanes at all. But one extra lane here or there probably doesn't matter much.

So, I take offense with phrases such as "not providing a high I/O" when detail is not provided to list how much IO they want. IO has been increased substantially in recent iterations. It just hasn't been enhanced enough for some users. So my question, how much is really needed?

My 2 interests are multiple high end GPUs for data science tasks, and very high speed ssd’s for some specific database stuff. Im not sure if either upcoming consumer solutions gets me there, although maybe pci5 for GPU isnt so important when using nvlink (assuming 4090 supports that)

 

[shady28]

I'm not sure why you need sources for additional IO on Alder Lake as it has been public knowledge for quite some time. But here goes.

• Rocket Lake: https://extremehw.net/all-reviews/11900k-z590-overclocking-guide/
• Alder Lake: https://i.pcmag.com/imagery/articles/00pFcBd5Oh7XFo7rV30jPxY-7.fit_lim.size_768x.jpg
• Raptor Lake: https://cdn.videocardz.com/1/2022/07/Intel-Raptor-Lake-S-PCH.jpg

For IO, Alder Lake:

• Switched from 1x16 PCIe 4.0 to 1x16 PCIe 5.0 directly from the CPU.
• Went from 3 DDI ports to 4 DDI ports directly from the CPU. Just put in a cheap DDI to USB converter and you can run an additional USB drive direct from the CPU and doesn't impact the bandwidth going between the CPU and the chipset.
• Went from x8 DMI 3.0 to x8 DMI 4.0 on the connection from the CPU to the chipset.
• Went from 24 PCIe 3.0 ports to 28 PCIe ports (12 PCIe 4.0 and 16 PCIe 3.0) on the chipset.
• Went from 6 SATA 6 Gb/s ports to 8 SATA 6 Gb/s ports on the chipset.
• Went from 3 USB 3.2 2x2 ports to 4 USB 3.2 2x2 ports on the chipset.

For IO, Raptor Lake:

• Adds additional PCIe 4.0 ports on the chipset (quantity added not yet revealed).
• Adds additional USB 2x2, PCIe 3.0, and SATA 3.0 ports on the chipset (quantity added not yet revealed).
• Is now fully Thunderbolt 4.0 compliant.

I could go into really minor details like the sound no longer being on the PCIe lanes at all. But one extra lane here or there probably doesn't matter much.

So, I take offense with phrases such as "not providing a high I/O" when detail is not provided to list how much IO they want. IO has been increased substantially in recent iterations. It just hasn't been enhanced enough for some users. So my question, how much is really needed?

I'm not going to waste time arguing a point that is frankly obvious with you, when you clearly didn't read my earlier post.

You're spouting off a bunch of things you can plug in. That's great, but those things are all constrained by the link to the chipset.

If they go to PCIe 5.0 x4 off the chipset, the links upstream to the CPU need to be improved. AMD is in even worse shape with their current X570 chipsets as they have half the bandwidth of Z690 from chipset to CPU.

Try doing the math on this and see how that works out.

 

[IntelUser2000]

Chances of all that happening at max rates are very, very slim. Also for storage it's usually SATA or NVMe and not both. SATA and Ethernet requirements are pretty small. The NVMe bandwidth is with sequential, QD32, T8+ scenarios and most of the time far lower even for transfer.

So while it does look congested, nowhere as critical.

 

[dnavas]

So while it does look congested, nowhere as critical.

Disagree, in this sense -- it's critical if you're attempting to position your desktop solutions as replacements for DIY HEDT. It's fine to claim that mainstream usecases are unlikely to bottleneck for significant portions of time on lack of I/O, but if I want to run zfs across 8 nvme devices, route that bandwidth to a coprocessor ("graphics") card and send that data to be further processed elsewhere, I don't want to bottlenecked by the tradeoffs that go into satisfying mainstream markets.

 

[Tuna-Fish]

If they go to PCIe 5.0 x4 off the chipset, the links upstream to the CPU need to be improved. AMD is in even worse shape with their current X570 chipsets as they have half the bandwidth of Z690 from chipset to CPU.

AMD has the benefit of having more IO available directly from the CPU. On AM5, there are 2x4 lanes of PCIe 5.0 from the CPU available for 2 M.2 drives, and iirc 4 USB 3.2 gen 2.

I think once Intel brings the PCH on the socket with Meteor lake, this bottleneck will vanish.

Disagree, in this sense -- it's critical if you're attempting to position your desktop solutions as replacements for DIY HEDT. It's fine to claim that mainstream usecases are unlikely to bottleneck for significant portions of time on lack of I/O, but if I want to run zfs across 8 nvme devices, route that bandwidth to a coprocessor ("graphics") card and send that data to be further processed elsewhere, I don't want to bottlenecked by the tradeoffs that go into satisfying mainstream markets.

Really agree with you here. The defining feature of HEDT for the people who are willing to pay the premium for it is often not the performance, but the connectivity. I really wish Intel got seriously back into this market, because AMD is now content to let TR lag almost a full cpu release cycle behind their desktop CPUs.

 

[CakeMonster]

AMD has the benefit of having more IO available directly from the CPU. On AM5, there are 2x4 lanes of PCIe 5.0 from the CPU available for 2 M.2 drives, and iirc 4 USB 3.2 gen 2.

Can you actually run 2 of those NVME in PCIE5 simultaneously? I thought there wasn't enough lanes if combined with PCIE x16 and other devices.

 

[shady28]

AMD has the benefit of having more IO available directly from the CPU. On AM5, there are 2x4 lanes of PCIe 5.0 from the CPU available for 2 M.2 drives, and iirc 4 USB 3.2 gen 2.

If you go directly off the CPU on a Zen 4 chip for 16X PCIe 5 GPU, and two PCIe 5 x4 m.2 devices, you won't have anything to connect to the chipset.

Zen 5 is likely to be :
PCI 5 x16 GPU to CPU
1 PCI 5 x4 m.2 to CPU
1 PCI 5 x4 to Chipset

Everything else you're connecting - Network, USB ports, Additional m.2 devices, bluetooth and so on will go across that one PCI 5 x4 link.

That PCIe 5 x4 link has exactly the same bandwidth as Intel's current DMI 4.0 x8 link to the chipset.

I would expect both platforms links to be improved in some way to effectively support PCIe 5 devices off the chipsets.

 

[AtenRa]

I'm not going to waste time arguing a point that is frankly obvious with you, when you clearly didn't read my earlier post.

You're spouting off a bunch of things you can plug in. That's great, but those things are all constrained by the link to the chipset.

If they go to PCIe 5.0 x4 off the chipset, the links upstream to the CPU need to be improved. AMD is in even worse shape with their current X570 chipsets as they have half the bandwidth of Z690 from chipset to CPU.

Try doing the math on this and see how that works out.

View attachment 65614

Actually AMD is just fine with X570, because ZEN 3 has 4 additional PCIe Gen4.0 lanes for storage and 4x USB 10Gbps inside the ZEN CPU SOC that doesnt need to go through the Chipset.
This way ZEN 3 + X570 can operate concurrently 2x NVMEs at PCIe 4.0 + 4x USBs 10Gbps at full speed without being bandwidth constrained.

With Intel AlderLake we can have 3x NVMEs (one from the CPU SOC + 2x from Chipset) or 2x NVMEs and 4x USBs at 10Gbps, the later exactly the same as AMD ZEN3 + X570.

 

[Tuna-Fish]

Can you actually run 2 of those NVME in PCIE5 simultaneously? I thought there wasn't enough lanes if combined with PCIE x16 and other devices.

In addition to the lanes reserved for the chipset, AM4 has 20 PCIe available from the CPU, AM5 has 24. In AMD AM5 diagrams, they assign 16 to GPU, 4 to 4x5.0 M.2, and the last 4 to either another M.2 slot, or a USB 4.0 controller. So if you want USB 4.0, you can only have one PCIe 5.0 M.2 from the CPU, and if you don't need it, the motherboard can support 2. In the recent "meet the expert" motherboard reveal, boards supporting multiple M.2s from the CPU were shown.

If you go directly off the CPU on a Zen 4 chip for 16X PCIe 5 GPU, and two PCIe 5 x4 m.2 devices, you won't have anything to connect to the chipset.

You are incorrect. AM5 socket has 28 PCIe lanes total, of which 4 always connect to the chipset.

 

[shady28]

Actually AMD is just fine with X570, because ZEN 3 has 4 additional PCIe Gen4.0 lanes for storage and 4x USB 10Gbps inside the ZEN CPU SOC that doesnt need to go through the Chipset.
This way ZEN 3 + X570 can operate concurrently 2x NVMEs at PCIe 4.0 + 4x USBs 10Gbps at full speed without being bandwidth constrained.

With Intel AlderLake we can have 3x NVMEs (one from the CPU SOC + 2x from Chipset) or 2x NVMEs and 4x USBs at 10Gbps, the later exactly the same as AMD ZEN3 + X570.

You have far more bandwidth to Z690 chipset than X570 - double. 128Gbps vs 64 Gbps. The 4x 10mbit USB off the CPU helps but doesn't negate that.

Once you use that PCIe 4 x4 nvme off the chipset, if it is a fast nvme, you are constrained off the chipset. Your network connection, any SATA drives, bluetooth devices, are also on the chipset along with any additional USB ports.

But in both cases, to run PCIe 5 nvme off the chipset they need more bandwidth.